Introduction VHDL is a hardware description language HDL

Introduction VHDL is a hardware description language (HDL) We use VHDL to write a program A VHDL program describes hardware Just like a schematic describes hardware A VHDL program describes a chip An HDL program is used to develop a chip Design Synthesis Simulation of chip Intel 8 -Core Xeon 7500 die with 2. 3 billion transistors Why an HDL program, why not schematics ? Real life circuits are too complex to be designed (described) by schematics There would be too many and complex schematics

Introduction VHDL was developed in the 1980 s under Department of Defense (Do. D) sponsorship Mandated for federally-sponsored VLSI designs VHDL stands for ? VHSIC Hardware Description Language VHSIC : Very High Speed Integrated Circuit VHSIC was a Do. D research program to encourage research on high-speed integrated circuit (chip) technologies Today VHDL is widely used across the industry, around the world Established as IEEE standard IEEE 1076 in 1987 Extended in IEEE standard IEEE 1164 in 1993 In 1996, IEEE 1076. 3 became a VHDL synthesis standard

Introduction VHDL has ADA flavour ADA is a software language developed under the Do. D sponsorship in the 1980 s Another common HDL language : Verilog HDL Verilog has C flavour Knowing one HDL language helps one learn another HDL language faster Page 3

Introduction A VHDL program is a collection of modules Top-down design (hierarchical designs) for large projects Designs described at various levels of abstraction More details at lower levels Block-based (modular) design Team-based design Each team member works on a different block (module) Core-based design Complex blocks (modules) can be licensed as VHDL programs Page 4

Language Overview : Basics Software : Statements are executed sequentially The sequence of statements is significant, since they are executed in that order Java, C++, C, Ada, Pascal, Fortran, … Hardware : Events happen concurrently A software language cannot be used for describing and simulating hardware Concurrent software languages cannot be used either Because we do not have powerful tools yet Programs in C/C++, etc. will be converted to hardware in the future It is already done for Matlab Lab. VIEW C++ Modified C++ language (System. C) C Catapult C from Mentor Graphics works on ANSI C++ and System. C Vivado from Xilinx works on C First these programs are converted to HDL programs and then to hardware CS 2204 Digital Logic & State Machine Design Spring 2014 Page 5

Language Overview : Basics VHDL is STRONGLY typed VHDL is not case sensitive “A” or “a” does not matter IBM BG/Q supercomputer microprocessor die with 1. 47 Billion transistors A VHDL program describes a digital system A digital system consists of blocks A VHDL program is a collection of modules A module consists of an entity and an architecture CS 2204 Digital Logic & State Machine Design Spring 2014 Page 6

Language Overview : Module Entity: shows inputs and outputs The black box view of the module Architecture : internal description : implementation It can be written in one of three different detail levels Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) CS 2204 Digital Logic & State Machine Design Spring 2014 Page 7

Language Overview : Module Sound the alarm if A VHDL program A text file (caralarm. vhd) the engine is on and the belt is not fastened A Schematic A schematic sheet (caralarm. sch) entity declarations architecture definition engine AND alarm NOT belt alarm = engine belt CS 2204 Digital Logic & State Machine Design Spring 2014 Page 8

library IEEE; use IEEE. std_logic_1164. all; entity caralarm is port ( engine: in STD_LOGIC; belt: in STD_LOGIC; alarm: out STD_LOGIC ); Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) library IEEE; entity caralarm is port ( engine: in STD_LOGIC; belt: in STD_LOGIC; alarm: out STD_LOGIC ); Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) Language Overview : Xilinx VHDL Programs for Car Alarm Circuit end caralarm; architecture caralarm_dataflow of caralarm is begin alarm <= engine and not belt ; alarm <= ‘ 1’ when engine = ‘ 1’ and belt = ‘ 0’ end caralarm_dataflow ; else ‘ 0’ ; end caralarm_dataflow ; CS 2204 Digital Logic & State Machine Design Spring 2014 Page 9

Language Overview : Full Adder VHDL Program Data-flow description of the Full Adder circuit : Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) ki mi ci Full Adder si si = ki mi ci + ki mi ci co = ki mi + ki ci + mi ci co CS 2204 Digital Logic & State Machine Design Spring 2014 Page 10

Language Overview : VHDL System Description A VHDL program describes a system A system is a digital system A system is a collection of one or more modules A module consists of an entity and an architecture CS 2204 Digital Logic & State Machine Design Spring 2014 Page 11

Language Overview : Design Flow VHDL compiler analyzes VHDL code for syntax errors and checks for compatibility with other modules Synthesizer converts VHDL program to a circuit with components Place and route fits the circuit to a die CS 2204 Digital Logic & State Machine Design Spring 2014 Page 12

VHDL Details : Entity Syntax The entity describes the black-box view The entity declares ports Inputs and outputs Digital circuit input signals Digital circuit output signals Syntax : entity caralarm is port ( engine: in STD_LOGIC; belt: in STD_LOGIC; alarm: out STD_LOGIC ); end caralarm entity-name is port (signal-names : mode signal-type ; …. signal-names : mode signal-type) end entity-name ; CS 2204 Digital Logic & State Machine Design Spring 2014 Page 13

VHDL Details : Architecture Syntax The architecture describes the internal operations By means of concurrent statements that use Signals inherited from the entity Variables used in functions, procedures and processes architecture-name of entity-name is type declarations signal declarations constant declarations function definitions component declarations begin architecture caralarm_dataflow of caralarm is concurrent statement begin alarm <= engine and not belt ; …. end caralarm_dataflow ; concurrent statement end architecture-name ; CS 2204 Digital Logic & State Machine Design Spring 2014 Page 14

VHDL Details : Full Adder Example entity-name is port (signal-names : mode signal-type ; …. . signal-names : mode signal-type) ; end entity-name ; architecture-name of entity-name is type declarations signal declarations constant declarations function definitions component declarations begin concurrent statement …. concurrent statement end architecture-name ; CS 2204 Digital Logic & State Machine Design Spring 2014 Page 15

VHDL Details : Types are required for every © IBM Signal Variable Function parameter Function result IBM dual-core Blue. Gene/L microprocessor die & its chip Type specifies a set/range of values for an object and a set of operators associated with it Predefined types User defined types Types must match in Assignment statements Comparisons Function calls CS 2204 Digital Logic & State Machine Design IBM Blue. Gene/L Supercomputer Spring 2014 Page 16

VHDL Details : Types Predefined types bit_vector boolean character integer real string time Intel dual-core Itanium 2 1. 72 -billiontransistor die & its wafer User-defined types Most commonly used one : Enumerated types CS 2204 Digital Logic & State Machine Design Spring 2014 Page 17

VHDL Details : Types Enumerated type is defined by listing its values User defined enumerated type : type-name is (value-list) ; type COLOR is (RED, ORANGE, YELLOW, BLUE, INDIGO, VIOLET) ; Subtypes of a type allowed : subtype-name is type-name start to end ; subtype LONGWAVE is color RED to YELLOW ; subtype-name is type-name start downto end ; Constants are allowed : constant-name : type-name : = value ; constant BUS_SIZE : integer : = 32 ; CS 2204 Digital Logic & State Machine Design Spring 2014 Page 18

VHDL Details : Predefined Operators Boolean operations And Or Nand nor xnor Not AND OR NAND NOR Exclusive NOR Complement Intel Xeon E 7 10 -core die at 32 nm process with 2. 6 billion transistors AMD Bulldozer 8 -core die with 1. 2 billion transistors CS 2204 Digital Logic & State Machine Design Intel Xeon E 7 wafer Spring 2014 Page 19

VHDL Details : Predefined Operators Integer operations + addition subtraction * multiplication / division modulo division rem modulo remainder absolute value ** exponentiation Cray Titan Supercomputer the 2 nd fastest computer in the world with AMD and TESLA chips 7. 1 Billion transistors NVIDIA TESLA GPU chip World’s densest chip CS 2204 Digital Logic & State Machine Design Spring 2014 Page 20

VHDL Details : Libraries keep information about a project The collection of libraries maintains the state of the design Intermediate files used in analysis, simulation and synthesis Previously analyzed entities and architectures Entity and architecture definitions for different modules can be in different files IBM Power 7 8–core die with 1. 2 billion transistors CS 2204 Digital Logic & State Machine Design Spring 2014 Page 21

VHDL Details : Library Compiler maintains a “work” library VHDL compiler generated information about a project To keep track of definitions via entity and architecture names It also contains analysis results No need to explicitly include in the VHDL program Library work ; Resource library contains shared definitions IEEE standard definitions library must be included in the VHDL program Library ieee ; CS 2204 Digital Logic & State Machine Design Spring 2014 Page 22

VHDL Details : Package A package contains definitions of objects Signal Type Constant Procedure Component declarations Standard logic defined by a “package” IEEE 1164 STD_LOGIC Intel 8 -Core Poulson (Itanium) die with 3. 1 billion transistors Must be included in the VHDL program Keyword “use” needed to specify a package Use ieee. std. logic. 1164. all Uses all definitions in the ieee library containing package std. logic. 1164 CS 2204 Digital Logic & State Machine Design Spring 2014 Page 23

VHDL Details : Standard Logic Types Commonly used IEEE-1164 types: STD_LOGIC (one bit) STD_LOGIC_VECTOR(range) (multi-bit vector) INTEGER (built-in integer type) library IEEE; Compiler knows where to find this (system-dependent) use IEEE. std_logic_1164. all; entity caralarm is Library name port ( engine: in STD_LOGIC; belt: in STD_LOGIC; Package name alarm: out STD_LOGIC); Use all definitions in package end caralarm; architecture caralarm_dataflow of caralarm is begin alarm <= engine and not belt ; end caralarm_dataflow ; CS 2204 Digital Logic & State Machine Design Spring 2014 Page 24

VHDL Details : Design Hierarchy Levels Structural Explicit components and the connections between them are defined It is the same as schematic design The VHDL programmer does schematic design in text Dataflow Most statements are assigning expressions to signals The tools are heavily involved in converting the text to hardware Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) Behavioral An algorithm that describes the circuit’s output is developed The tools may not be able to convert the text to hardware CS 2204 Digital Logic & State Machine Design Spring 2014 Page 25

VHDL Details : Structural Level A structural description is just like the schematic All components and interconnections are described It is a replica of the schematic ! It is not practical ! I 0 2 -to 4 DCD Y 0 Entity Part : Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) Y 1 Y 2 V 2 to 4 dec EN Y 3 I 1 CS 2204 Digital Logic & State Machine Design Spring 2014 Page 26

VHDL Details : Structural Description of a 2 -to 4 Decoder All components and interconnections are described Includes component statements A component statement is a concurrent statement Architecture Part : Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) 2 -to-4 Decoder Schematic Built-in library component Positional correspondence with component definition CS 2204 Digital Logic & State Machine Design Spring 2014 Page 27

VHDL Details : Dataflow Level Dataflow Description The detail is less compared with structural description Data dependencies described, not the components and connections Concurrency is used to model parallel operations of interconnected hardware elements Concurrent statements include assignment and select statements Structural (very detailed) Dataflow (less detailed) “when-else” Behavioral (least detailed) “with-select” CS 2204 Digital Logic & State Machine Design Spring 2014 Page 28

VHDL Details : Dataflow Description of a 3 -to-8 Decoder Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) Entity Part : CS 2204 Digital Logic & State Machine Design Y_L 0 A 0 V 74 x 138 Y_L 1 A 1 Y_L 2 A 2 3 -to-8 Y_L 3 Y_L 4 DCD G 1 Y_L 5 Y_L 6 G 2 A_L Y_L 7 G 2 B_L Spring 2014 Page 29

VHDL Details : Dataflow Description of a 3 -to-8 Decoder Architecture Part : Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) Y_L 0 A 0 V 74 x 138 Y_L 1 A 1 Y_L 2 A 2 3 -to-8 Y_L 3 Y_L 4 DCD G 1 Y_L 5 Y_L 6 G 2 A_L Y_L 7 G 2 B_L All assignment statements operate concurrently CS 2204 Digital Logic & State Machine Design Spring 2014 Page 30

VHDL Details : 3 -to-8 Decoder Translation to Hardware CS 2204 Digital Logic & State Machine Design Spring 2014 Page 31

VHDL Details : Behavioral Level Behavioral description May not be synthesizable Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) May lead to a very large circuit Primarily used for simulation Normally uses VHDL “processes” Each VHDL process executes in parallel with other VHDL processes and concurrent statements But “sequential” statements can be used within a process CS 2204 Digital Logic & State Machine Design Spring 2014 Page 32

VHDL Details : Process Sensitivity List Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) A sequence of sequential statements Activated when any signal in the sensitivity list changes Primarily a simulation concept, but can be synthesized CS 2204 Digital Logic & State Machine Design Spring 2014 Page 33

VHDL Details : Behavioral Description of a 3 -to-8 Decoder Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) A 0 A 1 A 2 G 1 V 3 to 8 dec 3 -to-8 DCD G 2 G 3 CS 2204 Digital Logic & State Machine Design Spring 2014 Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Page 34

VHDL Details : Another Behavioral Description of a 3 -to-8 Decoder A 0 A 1 A 2 G 1 V 3 to 8 dec 3 -to-8 DCD G 2 G 3 Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 May not be synthesizable May have a slow or inefficient realization Structural (very detailed) Dataflow (less detailed) Behavioral (least detailed) But fine for simulation and verification CS 2204 Digital Logic & State Machine Design Spring 2014 Page 35

VHDL Details : Is it always VHDL-only System Description ? One can mix schematic and VHDL Xilinx example 1. Start a schematic project 2. Write a VHDL program 3. Convert the VHDL program to a Xilinx macro (Custom Design Block, CDB) 4. The macro is appended to the component library list 5. Place the CDB in the schematic just like any other Xilinx component CS 2204 Digital Logic & State Machine Design Spring 2014 Page 36

What is a process ? A process statement is a concurrent statement, but all statements contained in it are sequential statement (statements that executes serially, one after the other). The use of processes makes your code more modular, more readable, 37

The sensitivity list List of all signals that the process is sensitive to. Sensitive means that a change in the value of these signals will cause the process to be invoked. 38

For combinational logic the sensitivity list must be complete !!! process (a) variable a_or_b; begin a_or_b : = a or b; z <= a_or_b; end process; ----- since b is not in the sensitivity list, when a change occurs on b the process is not invoked, so the value of z is not updated (still “remembering” the old value of z) 39

Incomplete sensitivity list effect a b z (VHDL) z (gate level) 40

What to put in sensitivity list ? All signals you do a test on and all signals that are on the right side of an assignment. In other words all the signals you are “reading” in the value Don’t read and write a signal at the same time !!! 41

VHDL Object Types Constants Signals Variables Files 42

Constant You can think of it just as a name for a value reset_c : = ‘ 0’; bus_width_c : = 32; The value assigned to a constant cannot be changed (the location of memory that stores the value cannot be modified) Benefits: a better documented design. it is easier to update the design. But do not exaggerate !!! since you’ll have to remember all these 43 names you

Signals It is a physical signal (you can think of it like a piece of wire) A signal is a sequence of time-value pairs A signal assignment takes effect only after a certain delay (the smallest possible delay is called a “delta time”). It is possible to define global signals (signals that can be shared among 44

Variables Assignment to variables are scheduled immediately (the assignment takes effect immediately) If a variable is assigned a value, the corresponding location in memory is written with the new value while destroying the old value. This effectively happen immediately so if the next executing statement in the program uses the value of the variable, it is the new value that is used. Typically, variables are used as a local storage mechanism, visible only inside a process 45

Signals vs. Variables Signals assignments are scheduled after a certain delay d Variables assignments happen immediately, there is no delay 46

In 1 s 3 Signals vs. Variables z In 2 s 4 s 2 library IEEE; use IEEE. std_logic_1164. all; entity combo is port (In 1, In 2: in std_logic; z : out std_logic); end entity combo; Use variables for computing intermediate values architecture rtl of combo is variable s 1, s 2, s 3, s 4: std_logic; begin sig_in_proc: process (In 1, In 2) is begin s 1 : = not In 1; s 2 : = not In 2; s 3 : = not (s 1 and In 2); s 4 : = not (s 2 and In 1); z <= not (s 3 and s 4); end process sig_in_proc; end architecture rtl; 47

Signals vs. Variables -- Process 1 – Correct Coding Style proc 1: process (x, y, z) is variable var_s 1, var_s 2: std_logic; begin var_s 1 : = x and y; var_s 2 : = var_s 1 xor z; res 1 <= var_s 1 nand var_s 2; end process; Process 2 – Incorrect proc 2: process (x, y, z) is begin sig_s 1 <= x and y; sig_s 2 <= sig_s 1 xor z; res 2 <= sig_s 1 nand sig_s 2; end process; signals variables 48

Delta Time architecture rtl of logic is signal a_or_b : std_logic; begin a_or_b <= a or b; -- a_or_b is scheduled @ t+D z <= a_or_b and c; -- z is scheduled @ t+2 D end rtl; NOTE: Here the two statements are concurrent (they are not embedded in a process) 49

Bad coding example: Delta time issues architecture bad of!!! logic is signal a_or_b : std_logic; begin logic_p: process(a, b, c) begin a_or_b <= a or b; z <= a_or_b and c; write end process; end bad; Do not “read” and “write” a signal at the same time !!! read 50

How to fix the bad coding example architecture good of logic is variable a_or_b : std_logic; begin logic_p: process(a, b, c) begin a_or_b : = a or b; z <= a_or_b and c; end process; end good; 51

Packages offers a mechanism to globally define and share values, types, components, functions and procedures that are commonly used. package declaration and package body 52

Subprograms Procedures can return more than one value (they can have both input and output parameters) Functions return always just one value (can have only input parameters) Example: conversion functions, 53

Attributes Info attached to VHDL objects Some predefined attributes: ‘left ‘right ‘high ‘low ‘length ‘event ‘range object the leftmost value of a type the greatest value of a type the number of elements in an array a change on a signal or variable the range of the elements of an array 54

Component (socket mechanism) Declare the name and interface of a “sub-unit”, to be used in the current level of design hierarchy. adder component adder port ( in_a, in_b: in std_logic_vector; z : std_logic_vector; carry: std_logic); end component; adder instance #1 55 adder instance #2

Elements of structural models Structural models describe a digital system as an interconnection of components An entity/architecture for each component must be independently available 56

Structural models are always “built” as follows: Define the components used in the design Describe the interconnection of these components Structural models can be easily generated (automatically) from 57

Hierarchy and Abstraction Structural modeling expresses the hierarchical nature of designs and provides a mechanism for the instantiation and reuse of cores 58

An example of structural modeling (1) shift_1 Clk Rst Load Init Data Q_net Q Qb shifter comp_1 A Test B EQ compare shiftcomp 59 Limit

An example of structural modeling (2) library ieee; use ieee. std_logic_1164. all; entity shiftcomp is port( Clk, Rst, Load: in std_logic; Init: in std_logic_vector(0 to 7); Test: in std_logic_vector(0 to 7); Limit: out std_logic); end shiftcomp; 60

An example of structural modeling (3) architecture structure of shiftcomp is component compare port(A, B: in std_logic_vector(0 to 7); EQ: out std_logic); end component; component shifter port(Clk, Rst, Load: in std_logic; Data: in std_logic_vector(0 to 7); Q: out std_logic_vector(0 to 7); Qb: out std_logic_vector(0 to 7)); end component; signal Q_net: std_logic_vector(0 to 7); begin COMP_1: compare port map (A => Q_net, B => Test, EQ => Limit); SHIFT_1: shifter port map (Clk => Clk, Rst => Rst, Load => Load, Data => Init, Q => Q_net, Qb => open); 61 end structure;

An example of structural modeling (4) -- 8 -bit barrel shifter library ieee; use ieee. std_logic_1164. all; entity shifter is port( Clk, Rst, Load: in std_logic; Data: in std_logic_vector(0 to 7); Q: out std_logic_vector(0 to 7); Qb: out std_logic_vector(0 to 7) ); end shifter; architecture rtl of shifter is begin reg: process(Rst, Clk) variable Qreg: std_logic_vector(0 to 7); begin if Rst = '1' then -- Async reset Qreg : = "0000"; elsif rising_edge(Clk) then if Load = '1' then Qreg : = Data; else Qreg : = Qreg(1 to 7) & Qreg(0); end if; Q <= Qreg; Qb <= not(Qreg); end process; end rtl; 62

An example of structural modeling (5) -- Eight-bit comparator library ieee; use ieee. std_logic_1164. all; entity compare is port( A, B: in std_logic_vector(0 to 7); EQ : out std_logic); end compare; architecture rtl of compare is begin EQ <= ‘ 1’ when (A = B) else ‘ 0’; end rtl; 63

ASSERT statement The ASSERT checks a boolean expression and if the value is true does nothing, else will output a text string to std output. It can have different severity levels: NOTE, WARNING, ERROR, FAILURE 64

COMPLEX TYPES: enumerated types TYPE color is (red, blue, yellow, green) ARRAY TYPE dbus is ARRAY (31 downto 0) of std_logic 65

COMPLEX TYPES: RECORD TYPE instruction is RECORD opcode: integer; src: integer; dest: integer; END RECORD 66

COMPLEX TYPES: FILE TYPE ram_data_file_t IS FILE OF INTEGER; FILE ram_data_file : ram_data_file_t IS IN “/claudio/vhdl/tb/ram. txt” 67

More on FILEs use std. textio. all; READ, WRITE, READLINE, WRITELINE, ENDFILE, … 68

Conclusions VHDL simplifies design of complex digital circuits VHDL allows core-based, top-down, team-based design VHDL and other HDLs will be used in foreseeable future as chip densities increase Sophomores will learn more VHDL/Verilog HDL in the future Eventually, C/C++/Matlab/Lab. VIEW/Java/… programs will be converted to hardware We will use C/C++/Matlab/Lab. VIEW/Java/… to design chips The key is developing powerful CAD tools CS 2204 Digital Logic & State Machine Design Spring 2014 Page 69

Future Directions : Moore’s Law will Continue to Hold In spite of claims that it will not continue to hold 3 -D transistors and 3 -d chips will help Moore’s law continue to hold www. ieee. org Power must be controlled CS 2204 Digital Logic & State Machine Design Spring 2014 Page 70

Future Directions : Intel ‘s Past Roadmap AMD Tahiti GPU chip with 4. 313 Billion transistors Intel 62 -core Xeon Phi processor 2012 5, 000, 000 CS 2204 Digital Logic & State Machine Design Spring 2014 Page 71

Future Directions : Power Density a Major Concern ! § Power Density was Increasing Exponentially ! 1000 Power was doubling every 4 years Rocket Nozzle Watts/cm 2 Nuclear Reactor 100 Pentium® 4 Pentium® III Pentium® II Hot plate 10 Pentium® Pro Pentium® i 386 i 486 Process Length 1 1. 5 m 1 m 0. 7 m 0. 5 m 0. 35 m 0. 25 m 0. 18 m 0. 13 m 0. 1 m 0. 07 m Courtesy : “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies” – Fred Pollack, Intel Corp. Micro 32 conference key note - 1999. Courtesy Avi Mendelson, Intel. CS 2204 Digital Logic & State Machine Design Spring 2014 Page 72

Future Directions : Power Density a Major Concern ! www. nanowerk. com § Power Density was Increasing Exponentially ! CS 2204 Digital Logic & State Machine Design Spring 2014 Page 73

Future Directions : Microprocessor speed The microprocessor speed was doubling every two years until multi-core processors emerged The processor speed was increasing 50% a year ! But, memory speed has been increasing 10 % a year ! Microprocessor speed for an application depends on Number of operations in the application (lower better) The quality of the code Number of parallel operations performed (higher better) Do more operations in parallel Perform each operation faster Because of Moore’s Law : transistors are smaller and wires are shorter Higher clock frequencies Until 2005 increasing the clock frequency was the main way to increase the speed Power consumption (heat generation) increases with the frequency Heat generation increases with the power consumption The chip has to be cooled by A heat sink or a fan or a liquid Since 2005 power consumption changed way to increase speed CS 2204 Digital Logic & State Machine Design Spring 2014 Page 74

Future Directions : Multi-Core Microprocessors Since 2005 microprocessor speed increase depends on Number of operations in the code (the quality of the code) Number of parallel operations performed Multi-core microprocessors with reduced frequency consume less power (generate less heat) Two/Four/Eight cores perform more operations in parallel The speed increase continues into the future with more cores on chip Clock frequency Number of cores per chip doubles every two years The memory can become a bottleneck The memory speed increases 10% a year More cores increase the demand on the memory The memory wall problem Parallel Programming has to be improved dramatically Parallel programming wall CS 2204 Digital Logic & State Machine Design Spring 2014 Page 75

Future Directions : Multi-Core Microprocessors § Double number of cores every two years Make sure to handle errors due to Alpha particles, neutrons Defective transistors Make sure to handle Power Wall Memory Wall Parallel programming Wall CS 2204 Digital Logic & State Machine Design Spring 2014 Page 76

CS 2204 Digital Logic & State Machine Design Scalable High Performance Main Memory System Using PCM Technology, Moinuddin K. Qureshi, et. al. , ISCA 2009, IBM From Intel www. anandtech. com Intel Technology Journal, November 2005 Future Directions : Intel & IBM Vision for Next 5 -8 Years Intel Spring 2014 Page 77

Future Directions : Next 5 -8 Years Applications Intel : Recognition, Mining, Synthesis as platform 2015 Workload Model (on massively parallel core chips) IBM : Presence information, knowing where and things are and how to best match them, people are sensorized Microsoft : Intention machine, computer predicts user intentions and delivers useful information CMU : Computational thinking, computer science based approach to solving problems, designing systems, understanding human behavior Traditional computing will continue A C/C++/Java/. . program for an application becomes Software A compiler generates the machine language program file A new type of computing A C/C++/Java/. . program for an application becomes Hardware A hardware compiler generates the GDS II file (the chip layout) The result is a custom chip CS 2204 Digital Logic & State Machine Design Spring 2014 Page 78

Future Directions : New Computing Types ? Any other new possibility ? A C/C++/Java/. . program for an application becomes Hardware A CAD tool generates the bit file to reconfigure the FPGA There can be more opportunities with FPGA chips ! Xilinx Vivado works on C They are increasingly used in commercial products ! FPGAs are becoming cost competitive with microprocessors FPGAs are becoming speed competitive with custom chips FPGAs are used for applications where Speed and programmability matter Latest FPGAs also have microprocessor cores They can run software as well The application is divided into software and hardware A machine code that is run by the cores and A bit file to program the reconfigurable areas Hybrid computing These cores can be hard or soft cores Hard means the manufacturer places a specific core on the die Soft means the user places any core any where on the die CS 2204 Digital Logic & State Machine Design Spring 2014 Page 79

Future Directions : New Computing Types A C/C++/Java/. . program becomes Xilinx Vivado works on C Part software and part hardware FPGA with cores and reconfigurable areas runs applications Software is run by processor cores and Hardware is in the reconfigurable area Hybrid computing When such an FPGA runs an application, some operations are in hardware and simultaneously some operations in software Processor core to run software Reconfigurable area to do operations in hardware These FPGAs are available now but we need much better tools Software tools (compilers) and CAD tools must merge Reconfigurable areas & cores can allow recovering from errors due to Alpha particles, neutrons Defective transistors CS 2204 Digital Logic & State Machine Design Spring 2014 Page 80

Future Directions : New Computing Types In summary, in the future a C/C++/Java/. . program will be converted to Software (like today) C++ programs become software, the machine code All operations happen in software ! Xilinx Vivado works on C Hardware C++ programs become custom chips All operations happen in hardware ! Hardware (better than what we have today) C/++ programs become hardware, the bit file for an FPGA All operations happen in hardware ! Part hardware and part software C/C++ programs run on FPGA chips with processors and configurable areas Some operations are in hardware and simultaneously some operations in software Software is run by processor cores A machine code that is run by processors Hardware is in the reconfigurable area A bit file to program the reconfigurable areas CS 2204 Digital Logic & State Machine Design Spring 2014 Page 81

Future Directions : Year 2020 SEMATECH : consortium of semiconductor manufacturers from America, Asia and Europe SEMATECH predictions for year 2020 (from its 2012 International Technology Roadmap for Semiconductors (ITRS) study) Clock speed : 5. 3 GHz Number of transistors on a microprocessor chip : 35 Billion 32 Gbit DRAM chips Process length : 11. 9 nm http: //www. sematech. org Make sure to handle errors due to Alpha particles, neutrons Defective transistors CS 2204 Digital Logic & State Machine Design Spring 2014 Page 82

Future Directions : 2020 and Beyond A PC in 2020 ? Electronic with chips IBM Deep Blue 1997 Electronic with chips 30 cores + 480 special chips IBM Watson 2011 Electronic with chips 2880 cores & 0. 08 PFLOPS + 16 TB RAM Thinking ? CS 2204 Digital Logic & State Machine Design Same raw processing power as human brain 20 PFLOPS + 2. 5 Peta (1015) 33 Exa (1018) Bytes Spring 2014 Page 83

Future Directions : 2020 and Beyond There are three computers at or higher speed than the raw speed of the human brain Thinking ? NUDT Tianhe-2 supercomputer Fastest computer in world : 3, 120, 000 cores 1. 024 Peta Bytes of RAM memory 12. 4 Peta Bytes of disk space NUDT Tianhe-2 supercomputer with max speed of (54 PFLOPS) (54 x 1015 FLOPS) Third computer at or higher speed than human brain (54, 000, 000 floating-point operations a second, FLOPS) (54, 000, 000 real number calculations a second) It does not have same raw processing power as human brain because its memory size is smaller than human brain memory : 2. 5 PBytes – 33 Exa (1018) Bytes IBM Sequoia & Cray Titan are first two computers at or higher speed of human brain CS 2204 Digital Logic & State Machine Design Spring 2014 Page 84

Future Directions : 2020 and Beyond Future Computers That Are 'Normally Off' Advanced spin-transfer torque magnetoresistive random access memory (STT-MRAM) technology to create a new type of computer : A "normally off" one Spintronics couples magnetism with electronics at the quantum mechanical level ACM Tech. News April 14, 2014 CS 2204 Digital Logic & State Machine Design Spring 2014 Page 85

Future Directions : New Systems The first carbon nanotube computer has been built Only carbon nanotube transistors used From : Nature, September 25, 2013 IBM’s A braininspired computer powered by what it calls “electronic blood” BBC News, October 18, 2013 CS 2204 Digital Logic & State Machine Design Spring 2014 Page 86

Future Directions : Memcomputing Processing and memory on the same chip Passive electronic components that have the memory capability Both processing and nonvolatile memory capability ! Brain like, analog and self-healing computing on a chip Memristors : Components relating electric charge and magnetic flux The missing fourth electronic component Resistors, capacitors and inductors They have storage capability FPGAs can be implemented with memristors ! Memcapacitors They have storage capability Meminductors They have storage capability CS 2204 Digital Logic & State Machine Design Spring 2014 Page 87

Future Directions : Hybrid Switching Elements CMOL : A circuitry composed of CMOS and molecular nanodevices A closer look at FPGA-like reconfigurable logic circuits Interface between CMOS and nanodevices Figures from : Konstantin K. Likharev A larger view of FPGA-like reconfigurable logic circuits Two CMOS cells and a nanodevice CS 2204 Digital Logic & State Machine Design Spring 2014 Page 88

Future Directions : Possible New Structures Nanotechnology Programmable materials NEMS Bio NEMS Nano medicine Drug delivery Smart diagnosis 1 Watt supercomputer IBM Blue Gene/L molecular dynamics demo Quantum computing Molecular self assembly Testing of molecular structures Adaptive molecular structures Merger of bio and non-bio structures Synthetic biology CS 2204 Digital Logic & State Machine Design www. ibm. com Nanocomputing Spring 2014 Page 89

Future Directions : 2020 and Beyond Will hardware and software be developed separately like today ? How will software be developed for nano systems ? Quantum software ? Molecular software ? Biosoftware ? How will hardware be developed for nano systems ? VHDL or Verilog HDL or C++ or ? Developing tools is critical Simulation of protein molecules folding on a supercomputer Iron atoms on copper with electron movement CS 2204 Digital Logic & State Machine Design Spring 2014 Page 90

Future Directions : Possible New Structures Microelectromechanical systems, MEMS, with computing elements Microembedded systems Smart Dust at UC Berkeley Bio MEMS UC Berkeley Sensor & Actuator Center Micro bio/chemistry lab on a chip ≡ Bio chip Camera pill to make diagnosis in the body Sugar level detector in bloodstream Optical sensor in the retina to restore vision Biochip ≡ Lab-on-a-chip ≡ Microfluidic array The Biochip Group at Mesa+ CS 2204 Digital Logic & State Machine Design Spring 2014 Page 91

Future Directions : Medicine and Biology Medical and Biology fields use electronic devices with or without software today In future, these devices will be hybrid, i. e. electronic and bio/chemical ! Beam of light to reveal disease/virus markers IBM lab-on-a-chip to test diseases and viruses Biochips Lung-on-a-chip : Harvard University Organ on a chip !!! CS 2204 Digital Logic & State Machine Design Spring 2014 Page 92

Future Directions : Possible New Structures Microelectromechanical systems, MEMS, with computing elements Other structures that can be used for a number of different applications with or without computing elements Micromotors Microcameras Micromirrors Microlenses Microsensors Micromachines An all-optical computing chip with micromirrors and microlenses ? 3 -D nano-printing www. microfabrica. com CS 2204 Digital Logic & State Machine Design Spring 2014 Page 93

Future Directions : Possible New Structures Nanotechnology Bio NEMS NYU-Poly Research on Protein nanofibers Nano medicine Smart drugs Jin Montclare of Chemical & Biological Sciences with her colleagues Bio-degradable microprocessors Protein nanofibers can Improve drug delivery to treat cancers, heart disorders and Alzheimer's Aid in the regeneration of human tissue, bone and cartilage Protein nanofibers could point way to tinier and more powerful microprocessors Protein-based microprocessors CS 2204 Digital Logic & State Machine Design Spring 2014 Page 94

Future Directions : Possible New Structures Smart drugs Nano medicine Nanomotors Could Churn Inside of Cancer Cells to Mush : Penn State Human body : New frontier Small antennas on a microchip receive magnetic fields that propel chip through blood stream : Stanford CS 2204 Digital Logic & State Machine Design Spring 2014 Page 95

Future Directions : Medicine and Biology 1) Nanotube transistor will help bond people with devices • Seamless bioelectronic communication between living organisms and devices 2) Part-bio, part-electronic transistor devised § A nano-sized transistor in a cell-like membrane powered by cell § In future, transistor can monitor and treat diseases § It can relay information about disease-related proteins inside cell membrane § It can lead to new ways to read and influence brain or nerve cells Seamless marriage of biological and electronic structures Many medical applications ! Nanotechnology will help improve our lives ! Help for people with disabilities ! But, many ethical issues will emerge CS 2204 Digital Logic & State Machine Design Spring 2014 Page 96

Future Directions : Medicine and Biology Scientist infects himself with a computer virus A radio frequency ID (RFID) chip implanted into his left wrist RFID chip gave him secure access to buildings and his mobile phone He then introduced a computer virus into the RFID chip The virus contaminated system that was used to communicate with it This is a software virus ! There will be hardware viruses when we use programmable chips ! Experiment provides a glimpse at the problems of tomorrow Such implants will be used to increase the memory capacity or IQ of people ! Nano Bio Machinery will be a new cross-disciplinary field ! Biology, Chem/Chem. E, CS/Comp. E/EE, Medicine ! CS 2204 Digital Logic & State Machine Design Spring 2014 Page 97

Future Directions : Medicine and Biology Off the shelf, on the skin : Stick-on electronic patches for health monitoring IEEE Spectrum April 2014 CS 2204 Digital Logic & State Machine Design Spring 2014 Page 98

Future Directions : Medicine and Biology Demonstration of some of the smallest moving parts could lead to molecular-scale switches Molecular-scale machines IEEE Spectrum April 2014 CS 2204 Digital Logic & State Machine Design Spring 2014 Page 99

Future Directions : Medicine and Biology A lab-on-a-chip could quickly tell if an infection is the dreaded antibiotic-resistant MRSA Molecular diagnostic methods Food Safety Medical Diagnostics Environmental Testing Eliminating expensive & complicated laboratories Company : F 3 Microfluidics CS 2204 Digital Logic & State Machine Design Spring 2014 Page 100

Future Directions : Medicine and Biology Shrinking Chemical Labs Onto Optical Fibers Lab-on-fiber sensors could monitor the environment and hunt for disease inside your body IEEE Spectrum April 2014 Lab-on-a-chip sensors are ideal for use in rural clinics or at a patient’s bedside. But their widespread use for other tasks has long been stalled by seemingly insurmountable obstacles. For example, in wet environments—such as inside the body or outdoors—a chip’s metal conductors easily corrode or short, making the sensor unreliable. Many chips also contain materials such as arsenic that are toxic to humans. Their biggest drawback, though, is size. Today’s power sources, processors, and transmitters take up at least a few square centimeters—too big to squeeze through blood vessels. To overcome many of these problems, some researchers are seeking to replace a chip’s electronic circuits with optical ones. By using light rather than current to read chemical reactions, a photonic chip works reliably in aqueous solutions, is immune to electromagnetic radiation, tolerates a wide range of temperatures, and poses fewer risks to biological tissues. CS 2204 Digital Logic & State Machine Design Spring 2014 Page 101

Future Directions : Medicine and Biology Neuromorphic Computing 'Roadmap' Envisions Analog Path to Simulating Human Brain Neuromorphic computing FPAAs Professor Jennifer Hasler displays a field programmable analog array (FPAA) board that includes an integrated circuit with biological-based neuron structures for power -efficient calculation. Hasler’s research indicates that this type of board, which is programmable but has low power requirements, could play an important role in advancing neuromorphic computing. ACM Tech. News April 21, 2014 CS 2204 Digital Logic & State Machine Design Spring 2014 Page 102

Future Directions : Longer Term Predictions By 2019 a $1000 computer will match the processing power of the human brain Raymond Kurzweil, Kurzweil. AI. net, 9/1/1999 His keynote speech at the Supercomputing Conference (SC 06) in November 2006 The title of his talk is “The Coming Merger of Biological and Non-Biological Intelligence” Singularity point ? Brain downloads possible by 2050 Ian Pearson, Head of British Telecom’s futurology unit, CNN. com, 5/23/2005 Computers will be used as virtual brain extensions ? Direct brain - Internet link ? CS 2204 Digital Logic & State Machine Design Spring 2014 Page 103

Future Directions : Longer Term Predictions Hans Moravec, 1998 Many ethical issues will be facing you ! Being prepared will help ! CS 2204 Digital Logic & State Machine Design Spring 2014 Page 104