VHDL Basic Language Elements C Sisterna UNSJ Argentina

VHDL Basic Language Elements C. Sisterna UNSJ - Argentina

Identifiers A basic identifier: May only contain alphabetic letters (A to Z and a to z), decimal digits (0 to 9) and the underline character (_) Must start with an alphabetic letter May not end with an underline character May not include two successive underline characters VHDL is not case-sensitive No blank space(s) are allowed Examples: Same identifier Txclk, Tx. Clk, TXCLK, Tx. CLK Legal identifiers Rst, Three_State_Enable, CS_244, Sel 7 D Illegal identifiers _Set, 80 X 86, large#bits, m__RAM, add_ DSDA - C. Sisterna VHDL - Elements 2

Objects A object holds a value of some specified type and can be one of the three classes Declaration Syntax: object_class <identifier> : type [ : = initial_value]; Class signal variable constant DSDA - C. Sisterna Object identifier VHDL - Elements Type boolean std_logic/std_ulogic std_(u)logic_vector unsigned 3

Objects Each object has a type and a class The type indicates what type of data can be hold by the data object The class indicates what can be done with the data object Constant constant data_bus: integer : = 32; Variable variable flag: boolean : = true; constant setup_time: time : = 3 ns; variable add_bus: std_logict_vector (12 downto 0); Classes Signal signal reset : bit; signal my_start_up: std_logic; File DSDA - C. Sisterna VHDL - Elements 4

Objects Implicit declarations of data objects Ports of an entity: Signals Generics of an entity: Constants Formal parameters of functions and procedures: Constant or Signals Index of for … loop statements (integers) DSDA - C. Sisterna VHDL - Elements 5

Signal Class An Object of class signal can hold information not only about the value of the data, but also the time at which the signal takes the new value An Object of class signal holds the present value of the signal and the possible future values as well Different values can be assigned to a signal at different times using signal assignment statements I/O ports are also signals that carry data values, but they also provide an Interface to the external world Signals are used to connect concurrent elements (like wires) DSDA - C. Sisterna VHDL - Elements 6

Signal Declaration - Architecture Signal Declarations: A signal is declared in the declarative part of an architecture signal count_i: std_logic; Signal Name (identifier) DSDA - C. Sisterna Signal Type boolean std_logic/std_ulogic std_(u)logic_vector unsigned integer VHDL - Elements 7

Signal Declarations - Port Declarations Port declarations appear in the port section of an entity declaration. Each port declaration is seperated by semicolon from the others A port declaration has three parts: [Signal] reset_n: in std_logic[: = initial_value]; Signal Name Port Mode in out inout buffer DSDA - C. Sisterna Signal Type boolean std_logic/std_ulogic std_(u)logic_vector unsigned integer VHDL - Elements 8

Port Modes (Defined in the Entity) Mode in: cannot be assigned a value to, so it can only be read and it appears on the RHS of the signal assignment Mode out: can only be assigned to, so it can appear on the LHS of the signal assignment Mode inout: can be assigned to and be read, so in can appear on either side of an assignment. It is intended to be used only for bidirectional kind of I/O ports Mode buffer: can be assigned to and be read, so in can appear on either side of an assignment. However, do not use mode buffer ! DSDA - C. Sisterna VHDL - Elements 9

Port Modes (Defined in the Entity) DSDA - C. Sisterna VHDL - Elements 10

Simple Signal Assignment architecture example of entity_a is begin. . . count <= count + 1; carry_out <= (a and b) or (a and c) or (b and c); Z <= y; . . . Right Hand Side (RHS) Source Signal(s) Left Hand Side (LHS) Target Signal LHS Signal Type DSDA - C. Sisterna RHS Signal Type VHDL - Elements 11

Internal Signal Declarations entity test 1 is generic (bus_width: integer : = 16); port (. . ); end entity; architecture example of test 1 is signal counter: std_logic_vector(7 downto 0); signal flag: boolean; constant signal full_fifo: bit; signal addr: std_logic_vector(bus_width-1 downto 0); signal data: std_logic_vector(bus_width*2 -1 downto 0); . . . begin. . . end architecture; DSDA - C. Sisterna VHDL - Elements 12

Signals – Initial Values - Simulation All signal have an initial value by the simulator when simulation begins (elaboration phase of the simulation): Case 1: It can be assigned in the signal declaration signal ini_cnt: std_logic_vector(3 downto 0): = “ 1111”; Case 2: It will be given a value by default depending on the type of the signal: It will be the first value on the right of the declared type: for instance for type std_logic the default value assigned is ‘U’, for type bit is ‘ 0’ DSDA - C. Sisterna VHDL - Elements 13

Signals – Initial Values For synthesis, there is no hardware interpretation of an intial value -> SYNHESIS IGNORES INTIAL VALUES signal counter: std_logic_vector(7 downto 0): =“ 10101111”; signal enable : std_logic: = ‘ 0’; Simulation No Problem Big Problem ! Synthesis Problem Missmatch between SIMULATION & IMPLEMENTATION ! Designer is responsable for setting the Hardware in a known intial state DSDA - C. Sisterna VHDL - Elements 14

Port Modes – Reading an Output An output port declared as mode out can not be read How to solve this problem? entity and_nand is port( a, b : in std_logic; z, z_bar: out std_logic); end; architecture bad of and_nand is begin z <= a and b; z_bar <= not z; Error end; DSDA - C. Sisterna VHDL - Elements 15

Port Modes – Reading an Output Solution: Use of an intermediate (dummy) signal entity and_nand is port( a, b: in std_logic; z, z_bar: out std_logic); end; architecture bad of and_nand is signal int_sig: std_logic; begin int_sig <= a and b; z <= int_sig; z_bar <= not int_sig; end; DSDA - C. Sisterna VHDL - Elements 16

Variable Class A Data Object of class variable can hold a simple value of a specific type Variable takes a new value immediately Variables are used to hold intermediate values between sequential instructions (like variable in the conventional software languages) Variables are only allowed in process, procedures and functions A variable declared in a process is never reinitialized A sub-program (function/procedure) declared variable is initialized for each call to the subprogram DSDA - C. Sisterna VHDL - Elements 17

Variable Declaration and Assignment Variable declaration syntax: variable <identifier> : <type> [: =initial value]; architecture example of variable_usage is begin. . . process(…) variable counter: integer range 0 to 10; variable ASK: boolean; -- v. declaration begin. . . counter : = 5; -- v. assignment statement ask : = true; . . . DSDA - C. Sisterna VHDL - Elements 18

Constant Class An Object of class constant holds a single value of a specific type The value is assigned to the constant during its declaration and the value can not be changed Constant declaration: constant <identifier>: type : = value; DSDA - C. Sisterna VHDL - Elements 19

Constants - Examples architecture example of constant usage is constant bus_width: integer : = 16; constant GNDLogic: bit : = '0'; constant Ancho. Bus: integer : = 16; constant message: string: = “End of simulation"; constant error_flag: boolean : = true; constant Clk. Period: time: = 50 ns; constant rise_time: = 5 ns; entity CPU is generic (add_width: integer: = 16); -- implicit constant port(Input_CPU: in bit_vector(add_width-1 downto 0); Output_CPU: out bit_vector((add_width*2)-1 downto 0)); end CPU; DSDA - C. Sisterna VHDL - Elements 20

Basic Language Elements VHDL TYPES Cristian Sisterna, MSc

VHDL Data Object Types VHDL is referred to as a strongly typed language Every Object has a TYPE associated with it and there can never be any ambiguity about what type an Object is DSDA - C. Sisterna VHDL - Elements 22

VHDL Object & Type signal data_a: std_logic; signal data_b: bit; Object Class Type data_a <= data_b; DSDA - C. Sisterna VHDL - Elements -- error 23

VHDL Object’s Types Every Object in VHDL has a class and can hold a value that belongs to a set of values. This set of values are declared as a type VHDL has what is called “standard types”. These are predefined types A type has associated with it a set of values and a set of operations VHDL provides the facility to define new types by using type declarations and defining the set of operations DSDA - C. Sisterna VHDL - Elements 24

VHDL Data Types TYPES scalar integer access file composite record discrete floating-point physical array enumeration real time unconstrained array user defined severity_level std_ulogic character constrained array std_ulogic_vector bit_vector std_logic_vector boolean string std_logic bit DSDA - C. Sisterna Signed/unsigned VHDL - Elements 25

Types: Enumeration User Defined Declaration examples of user defined enumeration types: type alu_functions is (disable, add, sub, mult, div); type octal is (‘ 0’, ’ 1’, ‘ 2’, ‘ 3’, ‘ 4’, ‘ 5’, ‘ 6’, ‘ 7’); type my_state_machine is (rst, load, count, inc, light); alu_functions is an enumeration type that has a set of ordered values Usage examples signal alu_op: alu_function; variable last_digit: octal : = ‘ 0’; signal nxt_state, current_state: my_state_machine; alu_op nxt_state last_digit current_state nxt_state DSDA - C. Sisterna <= <= : = <= <= sub; load; ‘ 9’; rst; add; ------ correcto? correcto? VHDL - Elements 26

Types: Enumeration boolean Type The VHDL standard defines boolean type as follow: type boolean is (false, true); Type boolean is the built-in comparison type in VHDL All the comparison results are of boolean type DSDA - C. Sisterna VHDL - Elements 27

Types: Enumeration boolean Type signal sys_on : std_logic; signal sys_off: std_logic; . . . if (sys_on = sys_off) then std_logic boolean variable bandera: boolean; signal a, b : std_logic; . . DSDA - C. Sisterna bandera : = a < b; -- ? bandera : = a ; -- ? VHDL - Elements 28

Type: Enumeration severity level The VHDL standard defines severity_level type as follow: type severity_level is (NOTE, WARNING, ERROR, FAILURE); severity_level is an specific type used to either: report a problem, using note or warning elements report an error, using error or failure elements It’s only used within a VHDL code written for simulation purposes, such us a Test Bench. No synthesis implementation DSDA - C. Sisterna VHDL - Elements 29

Type: Enumeration severity level Usage example: stop_sim: process begin wait for run_time; assert false report "End simulation time reached" severity failure; end process stop_sim; DSDA - C. Sisterna VHDL - Elements 30

Type: Enumeration bit Type bit is the built-in logical type in the VHDL standard type bit is (‘ 0’, ’ 1’); Bit type has two values represented by the characters ‘ 0’ and ‘ 1’ (characters no numbers), that is why the single quotes are necessary. signal dato: bit; variable direccion: bit; dato <= ‘ 1’; direccion : = dato; DSDA - C. Sisterna VHDL - Elements 31

Scalar Types: Enumeration std_ulogic Type bit has several restrictions: • not possible to describe three-state • not possible to have several drivers for the same signal • not possible to assign unknown to a signal • not possible to assign don’t care to a signal In simulation models: • not possible to describe pull up (weak one) • not possible to describe pull down (weak zero) • Not possible to describe that the signal is uninitialized std_ulogic/std_logic type DSDA - C. Sisterna VHDL - Elements 32

Scalar Types: Enumeration std_logic Type type std_logic is( DSDA - C. Sisterna 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-' ); ----- Uninitialized Forcing Unknown Forcing 0 Forcing 1 High Impedance Weak Unknown Weak 0 Weak 1 Wild card VHDL - Elements 33

Subtypes A type defines a set of values. A subtype defines a restricted set of values from a base type. Using a subtype declaration makes clear which values of the base type are valid. Syntax: subtpye <identifier> is <subtype_indication>; type range simple_expression to/downto simple_expresion; DSDA - C. Sisterna VHDL - Elements 34

Subtypes Examples: subtpye mi_int is integer range 0 to 1024; subtpye small_int is integer range -128 to +127; subtype byte is std_logic_vector(7 downto 0); type byte 2 is array (7 downto 0) of std_logic; type byte 3 is std_logic_vector(7 downto 0); --right? subtype byte 4 is array(7 downto 0) of std_logic; --right? type byte is array(7 downto 0) of std_logic; signal a: byte; signal c: std_logic_vector(7 downto 0); a <= c; DSDA - C. Sisterna VHDL - Elements -- right? 35

Scalar Types: integer An integer type defines a type whose set of values fall within a specified integer range Minimum range –(231 -1) to +(231 -1) Type integer is the built-in numeric type, which represent integer values VHDL standard defines integer type as follow: type integer is range -2147483648 to +2147483747; DSDA - C. Sisterna VHDL - Elements 36

Scalar Types: integer In practice, all implementations of the language use the 32 -bit two’s complement range to implement an integer When declaring an object of type integer, either a range o a determined values has to be specified to avoid synthesis issues, since by default any integer is declared as a 32 -bit two’s complement integer range Examples: constant number_of_bits: integer : = 32; signal count: integer range 0 to 15; constant max_count: integer : = 15; signal bus_width: std_logic_vector(number_of_bits-1 downto 0; signal loads: integer; DSDA - C. Sisterna VHDL - Elements 37

Scalar Types: integer Subtypes A subtype is a restricted range of a type. There are two predefined subtypes of integer, one is called natural and the other called positive subtype natural is integer range 0 to integer’high; subtype positive is integer range 1 to integer’high; A signal declared to be a subtype of natural is in fact an integer All the operators that the integer type has; are inherited by its subtypes DSDA - C. Sisterna VHDL - Elements 38

Scalar Types: integer Synthesis interpretation of integers An integer type or subtype is represented by a bus of wires, with the number of wires in the bus depending on the range of the type or subtype If the type or subtype includes negatives numbers, the representation is in two’s complement The representation of integer types always includes zero, even if the range does not The two’s complement representation of signed numbers means that the implementation will allways be symmetrical around zero DSDA - C. Sisterna VHDL - Elements 39

Scalar Types - Physical Type Contains values that represent measurement of some physical quantity, like time, length, voltage o current The only predefined physical type is time Values of this type are expressed as integer multiples of a base unit Example type time is range <implementation defined> units fs; is ps = 1000 fs; s he ns = 1000 ps; t n us = 1000 ns; y s r ms = 1000 us; o f sec = 1000 ms; e p min = 60 sec; ty e hr = 60 min; m ti end units; e No DSDA - C. Sisterna es ! s o p r u p s u t VHDL - Elements 40

Composite Type A composite type respresents a collections of values Array: represent a collection of values all belonging to a single type Composite type Record: represent a collection of values that may belong to different types DSDA - C. Sisterna VHDL - Elements 41

Composite Type: Array An array is a collection of values that belongs to the same type Examples: signal data_bus: std_logic_vector(15 downto 0); type addresses is array (0 to 63) of bit; type DATA_WORD is array (7 downto 0) of std_ulogic; type ROM is array (0 to 15) of DATA_WORD; DSDA - C. Sisterna VHDL - Elements 42

Composite Type: Array An elements of an array can be accessed by specifying the value of the index in the array -- ADDRESSES(15) -> 16 th element of the array add_bit_16 <= addresses(15); Specific elements of an array can be accessed by specifying the range of the index in the array addr_middle_range <= addresses(16 to 31); addr_high_range <= addresses(32 to 63); addr_low_range <= addresses(0 to 15); DSDA - C. Sisterna VHDL - Elements 43

Composite Type: Array Synthesis For synthesis all the arrays must be constrained when they are declared (since they will be mapped onto hardware) signal my_slv_array: std_logic_vector(3 downto 0); -- constrained array of type bit -- descending range -- index from 3 downto 0 -- MSB is the leftmost bit -- Highest index is equal to 3 Other way: subtype slv_4 is array(3 downto 0) of std_logic; … signal my_bit_array: slv_4; DSDA - C. Sisterna VHDL - Elements 44

Composite Type : Array Concatenation There is on operator only dedicated to be used with arrays The Concatenation Operator: & & concatenates two array to form a longer array in any of the following ways: Concatenate two arrays Concatenates one array with one element Concatenates one element with one array Concatenates two elements to form one array DSDA - C. Sisterna VHDL - Elements 45

Composite Type : Array Concatenation signal signal OP_CODE: std_logic_vector (0 to 4); My_CODE: std_logic_vector (4 downto 0); Final_Code: std_logic_vector ( ? ? ? ); ONE_Bit: std_logic; ONE_Nibble: std_logic_vector(3 downto 0); OP_CODE <= My_CODE; OP_CODE <= My_CODE & ONE_Bit; -- ? ? OP_CODE <= My_CODE(? ) & ONE_Bit; --? ? Final_Code <= OP_CODE & My_CODE; -- ? ? one_nibble <= op_Cod. E(1) & ‘ 0’ & OP_CODE(4) & FINAL_CODE(3); DSDA - C. Sisterna VHDL - Elements 46

Composite Type : Array Aggregates An aggregate is a set of comma-separated elements enclosed within parenthesis that are assigned to an array signal OP_CODE: std_logic_vector (4 downto 0); -- aggregate assignment positional notation OP_CODE <= (‘ 0’, ’ 1’, ’ 0’, ’ 1’); -- aggregate assignment named notation OP_CODE <= (2=>’ 1’, 4=>’ 1’, others=>’ 0’); The symbol => is used to associate the value on the left of the symbol to the indexed element on the right The others choice must be the last choice in the aggregate and selects all the remaining elements of the target DSDA - C. Sisterna VHDL - Elements 47

Arrays: examples and uses Elements of the array can be accessed either by static or dynamic index Static index: asc_vector(3) <= ‘ 1’; desc_vector(1) <= asc_vector(4); asc_vector(1 to 3)<= desc_vector(5 downto 3); --array slice Dynamic index: for i range 1 to 5 loop asc_vector(i) <= ‘ 0’; end loop; DSDA - C. Sisterna VHDL - Elements 48

Composite Type : Array Examples signal OP_CODE: std_logic_vector (1 to 5); signal My_CODE: std_logic_vector (5 downto 1); OP_CODE <= My_CODE; for i range 1 to 5 loop OP_CODE(i) <= my_code(i); end loop; DSDA - C. Sisterna VHDL - Elements 49

Arrays: Examples and uses signal signal mensaje: string (1 to 8): = “analysis”; bus: std_logic_vector(0 to 7): = x”aa”; mini_bus: std_logic_vector (0 to 4); codigo: std_logic_vector(1 to 5); operacion: std_logic_vector (5 downto 1); op_code: std_logic_vector (1 to 5); op_code <= “ 01001”; -- string literal op_code <= (‘ 0’, ’ 1’, ’ 0’, ’ 1’); -- aggregate assignment op_code <= (2=>’ 1’, 5=>’ 1’, others=>’ 0’); -- aggregate assignment operacion <= codigo; -- is this right? downto/to? DSDA - C. Sisterna VHDL - Elements 50

Arrays: Examples and uses signal signal mensaje: string (1 to 8): = “analysis”; bus: std_logic_vector (0 to 7): = x”aa”; mini_bus: std_logic_vector (0 to 4); codigo: std_logic_vector (1 to 5); operacion: std_logic_vector (5 downto 1); op_code: std_logic_vector (1 to 5); mini_bus <= bus(0 to 4); -- array slices bus <= mini_bus & “ 0101”; -- & concatenation operator mini_bus <= ‘ 0’ & bus(0) & bus(4 to 5); -- right? if (mini_bus(0)= bus(0)) then. . . DSDA - C. Sisterna VHDL - Elements 51

Multidimensional Arrays It is possible to define any number of dimensions for a data type. Arrays are used in the type declaration of multidimmensional data types type data 4 x 8 is array (0 to 3) of std_logic_vector(7 downto 0); type byte is array(7 downto 0) of std_logic; type data 4 x 8 is array(integer range 0 to 3) of byte; DSDA - C. Sisterna VHDL - Elements 52

Multidimensional Arrays architecture mult_dim_example of mult_array is type data 4 x 8 is array (0 to 3) of std_logic_vector(7 downto 0); signal d, e, f, g, h, i: data 4 x 8; signal b 1, b 2, 3, b 4: std_logic_vector(7 downto 0); begin d(0) <= “ 01110001”; d(1) <= “ 1010”; d(2) <= “ 0000”; d(3) <= “ 11111”; e <= (others => ‘ 0’); f(0) <= ‘ 1’; process(h) f(0) (1) <= ‘ 0’; begin G <= (b 1, b 2, b 3, b 4); loop 1: for n in 0 to 3 loop H <= (others=>b 1); i(n) <= h(n); . . . end lopp; end process; DSDA - C. Sisterna VHDL - Elements 53

Arrays: unsigned/signed package NUMERIC_STD is --================== -- Numeric array type definitions --==================== type UNSIGNED is array (NATURAL range <> ) of STD_LOGIC; type SIGNED is array (NATURAL range <> ) of STD_LOGIC; DSDA - C. Sisterna VHDL - Elements 54

Record Type ---------------------- Definitions for AMBA(TM) AHB Masters ---------------------type AHB_Mst_In_Type is record HGRANT: Std_ULogic; -- bus grant HREADY: Std_ULogic; -- transfer done HRESP: Std_Logic_Vector(1 downto 0); -- response type HRDATA: Std_Logic_Vector(HDMAX-1 downto 0); --rd data bus end record; DSDA - C. Sisterna VHDL - Elements 55

Record -- AHB master outputs type AHB_Mst_Out_Type is record HBUSREQ: Std_ULogic; -- bus request HLOCK: Std_ULogic; -- lock request HTRANS: Std_Logic_Vector(1 downto 0); -- transfer type HADDR: Std_Logic_Vector(HAMAX-1 downto 0); --addr bus HWRITE: Std_Ulogic; -read/write HSIZE: Std_Logic_Vector(2 downto 0); -- transfer size HBURST: Std_Logic_Vector(2 downto 0); -- burst type HPROT: Std_Logic_Vector(3 downto 0); --protection control HWDATA: Std_Logic_Vector(HDMAX-1 downto 0); -- wr data bus end record; DSDA - C. Sisterna VHDL - Elements 56

Qualifier Sometimes is not clear from the context what the type of a particular value is. So…. A qualifier is used to explicitly states which is the data type of an expression or data object datatype’expression or value type logic_level is (unknown, low undriven, high); type system_state is (unknown, busy, ready); logic_level’(unknown) system_state’(unknown) DSDA - C. Sisterna VHDL - Elements 57

Type Conversion - Casting VHDL does allow restricted type CASTING, that is converting values between related types datatype <= type(data_object); signal max_rem: unsigned (7 downto 0); signal more_t: std_logic_vector( 7 downto 0); max_rem <= more_t; max_rem <= unsigned(more_t); unsigned and std_logic_vector are both vectors of the same element type, therefore it’s possible a direct conversion When there is not relationship a conversion function is used DSDA - C. Sisterna VHDL - Elements 58

Type Conversion - Functions VHDL does have some built-in functions to convert some different data types (not all the types allow conversions) datatype <= to_type(data_object); signal internal_counter: integer range 0 to 15; signal count: std_logic_vector( 3 downto 0); count <= internal_count; Co. Un. T <= std_logic_vector(to_unsigned(internal_count, 4)); Function converts integer to unsigned Cast to slv unsigned slv DSDA - C. Sisterna VHDL - Elements 59

Type Conversion - Cast/Function From To Cast/Function std_logic_vector unsigned(std_logic_vector) std_logic_vector signed(std_logic_vector) unsigned std_logic_vector(unsigned) unsigned std_logic_vector(signed) signed unsigned(signed) unsigned integer to_integer(unsigned) signed integer to_integer(signed) integer unsigned to_unsigned(integer, no_of_bits) integer signed to_signed(integer, no_of_bits) DSDA - C. Sisterna singed(unsigned) VHDL - Elements 60

Type Conversion - Cast/Function DSDA - C. Sisterna VHDL - Elements 61

Alias An alias can be used to give alternative names to objects. An alias is used to facilitate the reading of the code signal flag_register: std_logic_vector(3 downto 0); -- registro de flags alias carry_flag: std_logic is flag_register(3); -- alias declaration alias overflow_flag: std_logic is flag_register(2); alias negative_flag: std_logic is flag_register(1); alias zero_flag: std_logic is flag_register(0); alias data: std_logic_vector(7 downto 0) is data_in(15 downto 8); DSDA - C. Sisterna VHDL - Elements 62

VHDL OPERATORS

VHDL Logic Operators DSDA - C. Sisterna VHDL - Elements 64

Boolean or Logic Operators All boolean operators have the same precedence Parenthesis must always be used to separate out the different boolean operators in an expression carry <= a and b or a and c or b and c; -carry <= (a and b) or (a and c) or (b and c); -- The only exception is the not operator zout <= not a and b; -- equivalent to zout <= (not a) and b; DSDA - C. Sisterna VHDL - Elements 65

Boolean or Logic Operators The inversion operands nand nor are not associative y 1 <= a nand b nand c; -- illegal y 1 <= (a nand b) nand c; -y 1 <= a nand (b nand c); -- Non inversion operands are associative parity <= d 0 xor d 1 xor d 2 xor d 3 xor d 4 xor d 5 xor d 6 xor d 7; DSDA - C. Sisterna VHDL - Elements 66

VHDL Relational Operators *numeric: types defined in the numeric_std package (unsigned, signed) and integer type. DSDA - C. Sisterna VHDL - Elements 67

Relational Operators All types have equality and inequality operators The result of relational operators is boolean type Boolean operators can be used with relational operators data <= a=0 and b=1; -- data should be type? Relational operatos have higher precedence than boolean operators. However, it is a good VHDL coding to use parenthesis: data <= (a=0) and (b=1); DSDA - C. Sisterna VHDL - Elements 68

VHDL Mathematical Operators *numeric: types defined in the numeric_std package: unsigned, and integer type. DSDA - C. Sisterna VHDL - Elements 69

VHDL Operators *numeric: types defined in the numeric_std package (unsigned, signed) and integer type. DSDA - C. Sisterna VHDL - Elements 70

VHDL Shift Operators DSDA - C. Sisterna VHDL - Elements 71

Operator Precedence 1 2 3 4 5 6 – – – Miscellaneous Multiplying Sign Adding Relational Logical ** , abs, not *, / , mod, rem +, +, -, & = , /=, <, <=, >, >= and, or, nand, nor, xor 3+4*5=? 3 – 4 + 5 = (3 – 4) + 5 = 4 y <= 2 * x ** 2 + -3 * x + -4; y <= (2 *(x ** 2)) +( -(3 * x)) + (-4); DSDA - C. Sisterna VHDL - Elements 72

Using Parenthesis When writing VHDL the designer must be aware of the logic structure being generated. One important point is the use of parenthesis when generating combinational logic. z <= a + b – c – d; z <= (a + b) – (c – d); Use parenthesis to control the structure of the synthesized logic DSDA - C. Sisterna VHDL - Elements 73

Basic Language Elements ATTRIBUTES

Attributes It’s way of extracting information from a type, from the values of a type or it might define new implicit signals from explicitly declared signals It’s also a way to allow to assign additional information to objects in your design description (such as data related to synthesis) Pre-defined Attributes Simulation & Synthesis DSDA - C. Sisterna User-defined/Synthesis Attributes Only Simulation VHDL - Elements 75

Predefined Attributes Syntax: <data_object/type/block>’attribute_identifier; DSDA - C. Sisterna VHDL - Elements 76

Array Attributes Array attributes are used to obtain information on the size, range and indexing of an array It’s good practice to use attributes to refer to the size or range of an array. So, if the size of the array is change, the VHDL statement using attributes will automatically adjust to the change DSDA - C. Sisterna VHDL - Elements 77

Array Attributes Array attributes are used to obtain information on the size, range and indexing of an array Attributes – Index Related A’left(array) Returns the index value corresponding to the left bound of a given array range A’right(array) Returns the index value corresponding to the right bound of a given array range A’ high(array) Returns the index value corresponding to the upper-most bound of a given array range A’low(array) Returns the index value corresponding to the lower bound of a given array range DSDA - C. Sisterna VHDL - Elements 78

Array Attributes – Value Related A’left Returns the left-most bound of a given type or subtype A’right Returns the left-most bound of a given type or subtype A’ high Returns the upper bound of a given type or subtype A’low Returns the lower bound of a given type or subtype A’length Return the length (number of elements of an array) A’ascending Return a boolean true value of the type or subtype declared with an ascending range DSDA - C. Sisterna VHDL - Elements 79

Array Attributes – Range Related A’range Returns the range value of a constrained array A’reverse_range Returns the reverse value of a constrained array DSDA - C. Sisterna VHDL - Elements 80

Array Attributes - Examples type bit_array variable I: DSDA - C. Sisterna is array integer: = (15 downto 0) of bit; bit_array'left(bit_array'range); -bit_array'right(bit_array'range); -bit_array'high(bit_array'range); -bit_array'low(bit_array'range); -- VHDL - Elements I I = = 15 0 81

Array Attributes - Examples type bit_array_1 is array (1 to 5) of bit; variable L: integer: = bit_array_1'left; -- L = 1 variable R: integer: = bit_array_1'right; 5 type bit_array_2 is array (0 to 15) of bit; variable H integer: = bit_array_2'high; type bit_array_3 -- R = -- H = 15 is array (15 downto 0) of bit; variable L: integer: = bit_array_3'low; -- L = 0 variable LEN: integer: = bit_array_3'length; -- L = 16 variable A 1: boolean : = bit_array_1'ascending; -- A 1 = true variable A 2: boolean : = bit_array_3'ascending; -- A 2 = false type states is (init, reset, cnt, end); signal Z, Y: states; Z <= estados'left; -- Z = init Y <= estados'right; -- Y = end DSDA - C. Sisterna VHDL - Elements 82

Array Attributes Use of the attributes range and reverse_range variable w_bus: std_logic_vector(7 downto 0); then: w_bus’range -- will return: while: w_bus’reverse_range DSDA - C. Sisterna VHDL - Elements 7 downto 0 -- will return: 0 to 7 83

Array Attributes function parity(D: std_logic_vector) return std_logic is variable result: std_logic : = '0'; begin for i in D'range loop result : = result xor D(i); end loop; return result; end parity; DSDA - C. Sisterna VHDL - Elements 84

Array Attributes for i in D'range loop. . . for i in D‘reverse_range loop. . . for i in D‘low to D’high loop. . . for i in D‘high to D’low loop. . . DSDA - C. Sisterna VHDL - Elements 85

User-defined/Synthesis Attributes VHDL provides designers/vendors with a way of adding additional information to the system to be synthesized Synthesis tools use this features to add timing, placement, pin assignment, hints for resource locations, type of encoding for state machines and several others physical design information The bad side is that the VHDL code becomes synthesis tools/FPGA dependant, NO TRANSPORTABLE …. DSDA - C. Sisterna VHDL - Elements 86

User-defined/Synthesis Attributes Syntax attribute attr_name: type; attribute attr_name of data_object: Object. Type is Attribute. Value; Ejemplos attribute syn_preserve: boolean; attribute syn_preserve of ff_data: signal is true; type my_fsm_state is (reset, load, count, hold); attribute syn_encoding: string; attribute syn_encoding of my_fsm_state: type is “gray”; DSDA - C. Sisterna VHDL - Elements 87

User-defined/Synthesis Attributes Example: type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0); signal ram: ram_type; attribute syn_ramstyle: string; attribute syn_ramstyle of ram: signal is “block_ram”; DSDA - C. Sisterna VHDL - Elements 88

User-defined/Synthesis Attributes Example: attribute pin_number of out_en: signal is P 14; attribute max_delay of in_clk: signal is 500 ps; attribute syn_encoding of my_fsm: type is “one-hot”; Synthesis Attribute DSDA - C. Sisterna VHDL - Elements 89