Hardware Description Language 1 B RAMAMURTHY 12172021 HDL

Hardware Description Language 1 B. RAMAMURTHY 12/17/2021

HDL 2 How do you specify this hardware design or model, its components/modules, instances and interface (ports) to the external world? How to automate the process? How do you design for testability/verifyability? Using a language that we can easily specify and understand. VHDL is a older language Verilog is commonly used 12/17/2021

HDL (contd. ) 3 The principal feature of a hardware description language is that it contains the capability to describe the function of a piece of hardware independently of the implementation. The great advance with modern HDLs was the recognition that a single language could be used to describe the function of the design and also to describe the implementation. This allows the entire design process to take place in a single language, and thus a single representation of the design. 12/17/2021

Verilog 4 The Verilog Hardware Description Language, usually just called Verilog, was designed and first implemented by Phil Moorby at Gateway Design Automation in 1984 and 1985. Verilog simulators are available for most computers at a variety of prices, and which have a variety of performance characteristics and features. Verilog is more heavily used than ever, and it is growing faster than any other hardware description language. It has truly become the standard hardware description language. 12/17/2021

Verilog 5 A Verilog model is composed of modules. A module is the basic unit of the model, and it may be composed of instances of other modules. A module which is composed of other module instances is called a parent module, and the instances are called child modules. comp 1 comp 2 system sub 3 12/17/2021

Verilog Design Concept 6 System instantiates comp 1, comp 2 instantiates sub 3 System comp 1 comp 2 sub 3 12/17/2021

Example 7 Primitives are instantiated in a module like any other module instance. For example, the module represented by this diagram would be instantiated: module example 1; ain wire n 1, n 2; n 2 n 1 bin reg ain, bin; and. Mod(n 1, ain, bin); not. Mod(n 2, n 1); endmodule 12/17/2021

Solutions using “assign” and “wire” 8 module AOI (input A, B, C, D, output F); /* start of a block comment wire F; wire AB, CD, O; assign AB = A & B; assign CD = C & D; assign O = AB | CD; assign F = ~O; end of a block comment */ // Equivalent. . . wire AB = A & B; wire CD = C & D; wire O = AB | CD; wire F = ~O; endmodule // end of Verilog code 12/17/2021

Net. List 9 module DEC 1 OF 8 (X 0 B, X 1 B, X 2 B, X 3 B, X 4 B, X 5 B, X 6 B, X 7 B, SL 0, SL 1, SL 2, ENB); output X 0 B, X 1 B, X 2 B, X 3 B, X 4 B, X 5 B, X 6 B, X 7 B; input SL 0, SL 1, SL 2, // select signals ENB; // enable (low active) //Module Description not // invert SL 0 -SL 2, N 1 (sl 0 b, SL 0), // & ENB N 2 (sl 1 b, SL 1), N 3 (sl 2 b, SL 2), N 4 (enbb, ENB); nand // select outputs NA 1 (X 0 B, sl 2 b, sl 1 b, sl 0 b, enbb), // (low active) NA 2 (X 1 B, sl 2 b, sl 1 b, SL 0, enbb), NA 3 (X 2 B, sl 2 b, SL 1, sl 0 b, enbb), NA 4 (X 3 B, sl 2 b, SL 1, SL 0, enbb), NA 5 (X 4 B, SL 2, sl 1 b, sl 0 b, enbb), NA 6 (X 5 B, SL 2, sl 1 b, SL 0, enbb), NA 7 (X 6 B, SL 2, SL 1, sl 0 b, enbb), NA 8 (X 7 B, SL 2, SL 1, SL 0, enbb); endmodule 12/17/2021

Module Definition + Gate Level Diagram 10 module abc (a, b, c, d, s 1, s 0); input s 1, s 0; output a, b, c, d; not (s 1_, s 1), (s 0_, s 0); and (a, s 1_, s 0_); and (b, s 1_, s 0); and (c, s 1, s 0_); and (d, s 1, s 0); endmodule 12/17/2021