VerilogHDL Reference Verilog HDL a guide to digital

Verilog-HDL Reference: Verilog HDL: a guide to digital design and synthesis, Palnitkar, Samir Some of slides in this lecture are supported by Prof. An-Yeu Wu, E. E. , NTU.

OUTLINE n n n Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function

Verilog HDL (continue) • Invented by Philip Moorby in 1983/ 1984 at Gateway Design Automation • Enables specification of a digital system at a range of levels of abstraction: switches, gates, RTL, and higher • Initially developed in conjunction with the Verilog simulator

Verilog HDL • Verilog- based synthesis tool introduced by Synopsys in 1987 • Gateway Design Automation bought by Cadence in 1989 • Verilog placed in public domain to compete with VHDL – Open Verilog International (OVI) IEEE 1364 -1995 and q q n revised version IEEE 1364 -2001 revised version IEEE 1364 -2005 For more details, please read the document of IEEE Standard for Verilog® Hardware Description Language

What is Verilog HDL ? n Mixed level modeling q Behavioral n n q Structural n n n n Algorithmic ( like high level language) Register transfer (Synthesizable) Gate (AND, OR ……) Switch (PMOS, NOMS, JFET ……) Single language for design and simulation Built-in primitives and logic functions User-defined primitives Built-in data types High-level programming constructs

Basic Conventions n n n Verilog is case sensitive – Keywords are in lowercase Extra white space is ignored – But whitespace does separate tokens Comments – One liners are // – Multiple lines /* */ – Comments may not be nested

OUTLINE n n Introduction Basics of the Verilog Language q q q n n Overview of Verilog Module Identifier & Keywords Logic Values Data Types Numbers & Negative Numbers Gate-level modeling Data-flow modeling Behavioral modeling Task and function

Overview of Verilog Module Test bench

Basic unit --Module module_name (port_name); port declaration data type declaration module functionality or structure endmodule

D-Flip. Flop module D_FF(q, d, clk, reset); output q; //port declaration input d, clk, reset; reg q; // data type declaration always @ (posedge reset or negedge clk) if (reset) q=1'b 0; else q=d; endmodule

Instance n n A module provides a template which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template The process of creating a object from module template is called instantiation The object is called instance

Instances module adder (in 1, in 2, cin, sum, cout); . . . . endmodule Mapping port positions module adder 8(. . ) ; adder add 1(a 1, b 1, 1’b 0, s 1, c 1) ; // assign by order add 2(. in 1(a 2), . in 2(b 2), . cin(c 1), . sum(s 2) , . cout(c 2)) ; // assign by name, the order is changeable Mapping names. . . endmodule

q T-Flip. Flop 。 d q module T_FF(q, clk, reset); clk ○ output q; input clk, reset; wire d; D_FF dff 0(q, d, clk, reset); // create an instance not n 1(d, q); endmodule

Identifier & Keywords n Identifier q q q User-provided names for Verilog objects in the descriptions Legal characters are “a-z”, “A-Z”, “ 0 -9”, “_”, and “$” First character has to be a letter or an “_” n n Example: Count, _R 2 D 2, FIVE$ Keywords q q q Predefined identifiers to define the language constructs All keywords are defined in lower case Cannot be used as identifiers n Example: initial, assign, module, always….

Hierarchical Modeling Concepts Top level block Subblock 1 Leaf cell Leaf cell Subblock 1 Leaf cell

Hierarchical Modeling Concepts Module ripple_carry_counter(q, clk, reset); output [3: 0] q; input clk, reset; T_FF tff 0(q[0], clk, reset); T_FF tff 1(q[1], q[0], reset); T_FF tff 0(q[2], q[1], reset); T_FF tff 0(q[3], q[2], reset); endmodule

Hierarchical Modeling Concepts module T_FF(q, clk, reset); output q; input clk, reset; wire d; D_FF dff 0(q, d, clk, reset); not na(d, q); endmodule

Hierarchical Modeling Concepts module D_FF(q, d, clk, reset); output q; input d, clk, reset; reg q; always @(posedge reset or negedge clk) if (reset) q=1’b 0; else q=d; endmodule

4 -bits Ripple Carry Counter Ripple carry counter T_FF (tff 0) D_ FF T_FF (tff 1) Inver ter D_ FF T_FF (tff 2) Inver ter D_ FF T_FF (tff 3) Inver ter D_ FF Inver ter

Exercise module Full. Add 4(a, b, carry_in, sum, carry_out); input [3: 0] a, b; input carry_in; output [3: 0] sum; output carry_out; wire [3: 0] sum; wire carry_out; Full. Add fa 0(a[0], b[0], carry_in, sum[0], carry_out 1); Full. Add fa 1(a[1], b[1], carry_out 1, sum[1], carry_out 2); Full. Add fa 2(a[2], b[2], carry_out 2, sum[2], carry_out 3); Full. Add fa 3(a[3], b[3], carry_out 3, sum[3], carry_out); endmodule

Exercise // Full. Add. V, 全加器 module Full. Add(a, b, carryin, sum, carryout); input a, b, carryin; output sum, carryout; wire sum, carryout; assign {carryout, sum} = a + b + carryin; endmodule

Exercise n Implement a 16 bits full adder by using 4 bits full adders.