02 VHDL VHDL VHDL Model Components Object Data
02 VHDL의 기본
VHDL의 기본 - 강의순서 ▣ VHDL Model Components ▣ Object ▣ Data Type ▣ Attribute ▣ Operator ▣ Statements ◈ Concurrent vs. Sequential Statements 2
Entity Declarations ▣ The primary purpose of the entity is to declare the signals in the component’s interface ▣ The interface signals are listed in the PORT clause ▣ PORT clause declares the interface signals of the object to the outside world ◈ Declaration syntax : PORT (signal_name : mode data_type); 4
Entity – Signal Mode ▣ The port mode of the interface describes the direction in which data travels with respect to the component ◈ In : data comes in this port and can only be read ◈ Out : data travels out this port ◈ Buffer : data may travel in either direction, but only one signal driver may be on at any one time ◈ Inout : data may travel in either direction with any number of active drivers allowed ; requires a Bus Resolution Function 5
Entity – Signal Type ▣ 1 bit signal: bit, std_logic ▣ 2 bit이상의 signal: bit_vector, std_logic_vector ◈ 2 bit -- bit_vector(1 downto 0) std_logic_vector(1 downto 0) ◈ 4 bit -- bit_vector(0 to 3) std_logic_vector(0 to 3) ◈ std_logic, std_logic_vector : IEEE 1164 Standard Signal Type으로 std_logic, std_logic_vector 이 사용될 때 는 아래의 문장이 Entity문장 전에 미리 사용 되어야 함. Library ieee; Use ieee. std_logic_1164. all; 6
Architecture Bodies ▣ Describe the operation of the component ▣ Consist of two parts : ◈ Declarative part -- includes necessary declarations Ø type declarations, signal declarations, component declarations, subprogram declarations ◈ Statement part -- includes statements that describe organization and/or functional operation of component Ø concurrent signal assignment statements, process statements, component instantiation statements architecture 동작표현이름 is [선언문] begin 동작 표현 end entity이름 7
Entity and Architecture ex. LIBRARY __library_name; USE __library_name. __package_name. ALL; ENTITY __entity_name IS PORT( __input_name, __input_name __input_vector_name __bidir_name, __bidir_name __output_name, __output_name ); END __entity_name; : INOUT : OUT STD_LOGIC; STD_LOGIC_VECTOR(__high DOWNTO __low); STD_LOGIC ARCHITECTURE a OF __entity_name IS SIGNAL __signal_name : STD_LOGIC; BEGIN -- Process Statement -- Concurrent Procedure Call -- Concurrent Signal Assignment -- Conditional Signal Assignment -- Selected Signal Assignment -- Component Instantiation Statement -- Generate Statement END a; 8
Simple VHDL Code : AND Gate Library ieee; Use ieee. std_logic_1164. all; Entity and_2 is port( a, b : in std_logic; y : out std_logic ); end and_2; Architecture dataflow of and_2 is begin y <= a and b; end dataflow; Signal Type으로 std_logic이 사용될 때는 항상 사용. Entity 문장 : 입력 a, b, 출력 y를 나타냄 Architecture Body : 회로의 설명 9
객체(Object) ▣ 값을 가질 수 있는 변수로 아래의 3가지 종류 ◈ Signals ◈ Variable ◈ Constants ▣ The scope of an object is as follows : 1. Objects declared in a package are available to all VHDL descriptions that use package 2. Objects declared in an entity are available to all architecture associated with that entity 3. Objects declared in an architecture available to all statements in that architecture 4. Objects declared in a process are available only within that process 10
객체(Object) - Signals ▣ Used for communication between VHDL components ▣ Real, Physical signals in system often mapped to VHDL signals ▣ All VHDL signal assignments require either delta cycle or user-specified delay before new value is assumed. ◈ Declaration syntax : SIGNAL signal_name : type_name [ : =value]; ◈ 사용 예 signal a, b : std_logic; 선언 a<= ‘ 1’; b<=‘ 0’; Signal a, b에 값 ‘ 1’, ’ 0’을 대입. 11
객체(Object) - Variable ▣ Provide convenient mechanism for local storage ▣ Scope is process in which they are declared ▣ All variable assignments take place immediately ◈ Declaration syntax : VARIABLE variable_name : type_name [ : =value]; ◈ 사용 예 variable a, b : std_logic; 선언 a : = ‘ 1’; b : =‘ 0’; Variable a, b에 값 ‘ 1’, ’ 0’을 대입. 12
객체(Object) - Constants ▣ Name assigned to a specific value of a type ▣ Allow for easy update and readability ◈ Declaration syntax : CONSTANT constant_name : type_name [ : =value]; ◈ 사용 예 constant bits 3_0 : std_logic_vector(2 downto 0) : = "000"; 선언 y<= bits 3_0; Signal y에 값 “ 000”을 대입. 13
Data Type ▣ Scalar Types ◈ Enumeration Type : BIT, BOOLEAN, CHARACTER ◈ Integer Type : INTEGER ◈ Floating : REAL ◈ Physical ▣ Composition Type ◈ Array Type ◈ Record Type 14
Data Type - Scalar Types(1) ▣ Enumeration Type ◈ type bit is (‘ 0’, ‘ 1’); ◈ type boolean is (false, true); ◈ type std_ulogic is ( ‘U’, ‘X’, ‘ 0’, ‘ 1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’); ◈ type std_logic is resolved std_ulogic; ▣ IEEE 1164 Standard Data Types ◈ ‘U’ : Uninitialized ‘X’ : Strong Unknown ◈ ‘ 0’ : Strong Logic 0 ‘ 1’ : Strong Logic 1 ◈ ‘Z’ : High Impedance ‘W’ : Weak Unknown ◈ ‘L’ : Weak Logic 0 ‘H’ : Weak Logic 1 ◈ ‘-’ : Don’t Care 15
Data Type - Scalar Types (2) ▣ Integer Type ◈ Minimum range for any implementation as defined by standard : -2, 147, 483, 647 to 2, 147, 483, 647 ▣ Floating type ◈ Minimum range for any implementation as defined by standard : -1. 0 E 38 to 1. 0 E 38 16
Data Type - Composition Type ▣ Array Type ◈ type byte is array (7 downto 0) of bit; byte형을 선언 ◈ signal a: byte; a를 byte로 선언 ◈ a <= “ 00001111”; a에 값 할당 17
Operators ▣ Defined precedence levels in decreasing order : ◈ Miscellaneous operators -- **, abs, not ◈ Multiplication operators -- *, /, mod, rem ◈ Sign operator -- +, ◈ Addition operators -- sll, srl, sla, sra, rol, ror ◈ Relational operators -- =, /=, <, <=, >, >= ◈ Logical operators -- AND, OR, NAND, NOR, XNOR 18
Attribute ▣ Attributes provide information about certain items in VHDL ◈ X’EVENT -- TRUE when there is an event on signal X ◈ X’LAST_VALUE -- returns the previous value of signal X ◈ Y’HIGH -- returns the highest value in the range of Y ◈ X’STABLE(t) -- TRUE when no event has occurred on signal X in the past ‘t’ time 19
02 -2 Statements
Statements - 강의순서 ▣ 병행(Concurrent) Statement ◈ Simple Assignment, Simple ◈ Signal Assignment, Conditional ◈ Signal Assignment, Selected ◈ Process Statement ▣ 순차(Sequential Statements) ◈ If Statement ◈ Case Statement ◈ For Loop Statement 21
Concurrent - Signal Assignment, Simple signal_name <= expression; y <= b; 1) b에 변화가 생길 때마다 b의 값이 y에 출력됨 2) Sensitivity List : b y <= a or b; 1) a 나 b에 변화가 생길 때마다 a or b의 값이 y에 출력됨. 2) Sensitivity List : a, b
Concurrent - Signal Assignment, Conditional signal <= expression 1 WHEN boolean_expression 1 ELSE expression 2 WHEN boolean_expression 2 ELSE expression 3; 1) boolean_expression 1= 참(True)이면 signal <= expression 1이 실행되며, 2) boolean_expression 2= 참(True) 이면 signal <= expression 2이 실행되며, 3) 위의 2가지 조건이 모두 성립하지않으면 signal <= expression 3이 실행된다.
Concurrent - Signal Assignment, Selected WITH expression SELECT signal <= expression 1 WHEN constant_value 1, expression 2 WHEN constant_value 2, expression 3 WHEN constant_value 3; 1) expression = constant_value 1 이면 signal <= expression 1이 실행되며, 2) expresion 1 = constant_value 2 이면 signal <= expression 2이 실행되며, 3) expresion 1 = constant_value 3 이면 signal <= expression 3이 실행된다.
Concurrent – Process Statement ▣ Process문은 하드웨어 모듈을 기술. ▣ Process문의 내부는 순차처리. ▣ 복잡한 알고리즘의 구현 시 편리 ◈ Declaration syntax : [Label: ] process [( Sensitivity List)] begin Sensitivity List에 적혀있는 신호에 변화생길 때 Sequential statements; end process [Label]; begin과 end process내의 문장을 실행
Sequential – Wait Statement wait on signal [, signal] wait until boolean_expression wait for time_expression Suspends the sequential execution of a process or subprogram (1) wait on a, b; (1) a, b에 변화가 생길 때까지 기다린다. (2) wait until ( x < 100 ); (2) X<100일 때까지 기다린다. (3) wait for 10 ns; (3) 10 ns동안 기다린다.
Sequential – Wait on vs. explicit sensitivity list wait on statement process begin y <= a and b; wait on a, b; end process; explicit sensitivity list process (a, b) begin y <= a and b; end process; ßProcess문을 사용하는 두가 지 방식 : 모두 가능함.
Sequential – IF Statement IF expression 1 THEN statement 1 -1; statement 1 -2; ELSIF expression 2 THEN statement 2 -1; statement 2 -2; ELSE statement 3 -1; statement 3 -2; END IF; 1) expression 1 = 참(True)이면 statement 1 -1, state 1 -2가 실행, 2) expression 2 = 참(True) 이면 statement 2 -1, state 2 -2가 실행, 3) 위의 2가지 조건 모두 성립하지않으면 statement 3 -1, state 3 -2가 실행,
Sequential – Case Statement CASE expression IS WHEN constant_value 1 => statement 1 -1; statement 1 -2; WHEN constant_value 2 => statement 2 -1; statement 2 -2; WHEN OTHERS => statement 3 -1; statement 3 -2; END CASE; 1) expression 1 = constant_value 1 이면 statement 1 -1, state 1 -2가 실행, 2) expression 1 = constant_value 1 이면 statement 2 -1, state 2 -2가 실행, 3) 위의 2가지 조건 모두 성립하지않으면 statement 3 -1, state 3 -2가 실행,
Sequential – For Statement loop_label: index_variable 의 값을 변해 FOR index_variable IN range LOOP statement 1; statement 2; END LOOP loop_label; 가면서 statement 1, statement 2를 반복적으로 실 행. 아래의 (a), (b)는 모두 같은 표현임. Range는 downto, to의 2가지 형태임. loop_Start: y(0) <= a(0) and b(0); FOR i IN 0 to 3 LOOP y(1) <= a(1) and b(1); y(i) <= a(i) and b(i); y(2) <= a(2) and b(2); END LOOP loop_Start; y(3) <= a(3) and b(3); (a) (b)
02 -3 VHDL 모델링
02 -3 -1 Dataflow Description
Dataflow - 2입력 AND Gate Library ieee; Use ieee. std_logic_1164. all; Entity and_2 is port( a, b : in std_logic; y : out std_logic ); end and_2; Architecture dataflow of and_2 is begin y <= a and b; end dataflow; Dataflow 방식은 부 울대수를 그대로 표 현 35
Dataflow - 2입력 OR Gate Library ieee; Use ieee. std_logic_1164. all; Entity or_2 is port( a, b : in std_logic; y : out std_logic ); end or_2; Architecture dataflow of or_2 is begin y <= a or b; end dataflow; 36
Dataflow - Andor_2 library ieee; use ieee. std_logic_1164. all; entity andor_2 is port( a, b, c : in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is signal t : std_logic; begin t<=a and b; y<=t or c; end a;
Dataflow – 4 bits OR gate library ieee; use ieee. std_logic_1164. all; Bus의 사용 entity or_4 bits is port( a, b : in std_logic_vector(3 downto 0); y : out std_logic_vector(3 downto 0) ); end or_4 bits; architecture xxx of or_4 bits is begin y <= a or b; end xxx;
Dataflow - Half Adder library ieee; Use ieee. std_logic_1164. all; Entity half_add is port( a, b : in std_logic; sum, c_out : out std_logic ); end half_add; Architecture dataflow of half_add is begin sum <= A xor B; c_out <= A and B; end dataflow; 문장의 순서는 무관
Dataflow - Full Adder library ieee; use ieee. std_logic_1164. all; entity fulladd is port( a, b, cin : in std_logic; s, cout : out std_logic); end fulladd; architecture a of fulladd is signal t 1, t 2, t 3 : std_logic; begin t 1 <= a xor b; t 2 <= a and b; t 3 <= t 1 and cin; s <= t 1 xor cin; cout <= t 2 or t 3; end a; 문장의 순서는 무관 t 1 t 2 t 3
Dataflow - Decoder 3_8 library ieee; use ieee. std_logic_1164. all; entity decoder 38_data is port( d 2, d 1, d 0 : in std_logic; y 0, y 1, y 2, y 3, y 4, y 5, y 6, y 7 : out std_logic); end decoder 38_data; architecture xxx of decoder 38_data is signal nd 2, nd 1, nd 0 : std_logic; Begin nd 2 <= not d 2; nd 1 <= not d 1; nd 0 <= not d 0; y 0<= nd 2 and nd 1 and nd 0; y 1<= nd 2 and nd 1 and d 0; y 2<= nd 2 and d 1 and nd 0; y 3<= nd 2 and d 1 and d 0; y 4<= d 2 and nd 1 and nd 0; y 5<= d 2 and nd 1 and d 0; y 6<= d 2 and d 1 and nd 0; y 7<= d 2 and d 1 and d 0; end xxx;
02 -3 -2 Structural Description
Structure - Andor_2 library ieee; use ieee. std_logic_1164. all; entity andor_2 is port( a, b, c : in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is And_2 선언 component and_2 port( a, b : in std_logic; y : out std_logic ); end component; component or_2 port( a, b : in std_logic; y : out std_logic ); Or_2 end component; 선언 signal t : std_logic; begin U 1 : and_2 port map ( a, b, t ); U 2 : or_2 port map( a=> t, b=>c , y=>y); end a; and_2. vhd, or_2. vhd는 미리 작성된 상태임.
Structure - Andor_2 library ieee; use ieee. std_logic_1164. all; entity andor_2 is port( a, b, c : in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is component and_2 port( a, b : in std_logic; y : out std_logic ); end component; component or_2 port( a, b : in std_logic; y : out std_logic ); end component; signal t : std_logic; begin U 1 : and_2 port map ( a, b, t ); U 2 : or_2 port map( a=> t, b=>c , y=>y); end a; 형 식 이 름 실 제 이 름 And_2 : 위치결합 방식 Or_2 : 이 름결합방 식
Structure – 4 bits adder library ieee; use ieee. std_logic_1164. all; tcout 1 entity add_4 bits is port( a, b : in std_logic_vector(3 downto 0); cin : in std_logic; sum : out std_logic_vector(3 downto 0); cout : out std_logic ); end add_4 bits; architecture a of add_4 bits is component fulladd port( a, b, cin : in std_logic; s, cout : out std_logic); end component; signal tcout 1, tcout 2, tcout 3 : std_logic; begin U 1 : fulladd port map( a(0), b(0), cin, sum(0), tcout 1); U 2 : fulladd port map( a(1), b(1), tcout 1, sum(1), tcout 2); U 3 : fulladd port map( a(2), b(2), tcout 2, sum(2), tcout 3); U 4 : fulladd port map( a(3), b(3), tcout 3, sum(3), cout); end a; tcout 2 tcout 3 Fulladd. vhd는 미리 작성된 상태임
Structure - Mux 8 X 1 Library ieee; Use ieee. std_logic_1164. all; entity mux 8_1 is port( a, b, c, d, e, f, g, h : in std_logic; s 2, s 1, s 0 : in std_logic; y : out std_logic); end mux 8_1; architecture xxx of mux 8_1 is component decoder 3_8 port( a, b, c : in std_logic; d 0, d 1, d 2, d 3, d 4, d 5, d 6, d 7 : out std_logic); end component; t(0) t(1) t(2) t(3) t(4) t(5) t(6) t(7) signal t : std_logic_vector(7 downto 0); signal d 0, d 1, d 2, d 3, d 4, d 5, d 6, d 7 : std_logic; begin Decoder 3_8. vhd는 U 1: decoder 3_8 port map( s 2, s 1, s 0, d 1, d 2, d 3, d 4, d 5, d 6, d 7); 미리 작성된 상태임 t(0) <= a and d 0; t(1) <= b and d 1; t(2) <= c and d 2; t(3) <= d and d 3; t(4) <= e and d 4; t(5) <= f and d 5; t(6) <= g and d 6; t(7) <= h and d 7; y <= t(0) or t(1) or t(2) or t(3) or t(4) or t(5) or t(6) or t(7); end xxx; Mixed Modelling : structure + dataflow
Structure – 4 bits Mux 8 X 1 Library ieee; Use ieee. std_logic_1164. all; Entity mux 81_4 bits is port( a, b, c, d, e, f, g, h : in std_logic_vector(3 downto 0); s 2, s 1, s 0 : in std_logic; y : out std_logic_vector(3 downto 0)); end mux 81_4 bits; Architecture a of mux 81_4 bits is component mux 8_1 port( a, b, c, d, e, f, g, h : in std_logic; s 2, s 1, s 0 : in std_logic; y : out std_logic); end component; begin U 0: mux 8_1 port map (a(0), b(0), c(0), d(0), e(0), f(0), g(0), h(0), s 2, s 1, s 0, y(0)); U 1: mux 8_1 port map (a(1), b(1), c(1), d(1), e(1), f(1), g(1), h(1), s 2, s 1, s 0, y(1)); U 2: mux 8_1 port map (a(2), b(2), c(2), d(2), e(2), f(2), g(2), h(2), s 2, s 1, s 0, y(2)); U 3: mux 8_1 port map (a(3), b(3), c(3), d(3), e(3), f(3), g(3), h(3), s 2, s 1, s 0, y(3)); end a;
02 -3 -3 Behavioral Description
Behavioral - Signal Assignment, Conditional library ieee; use ieee. std_logic_1164. all; entity mux 21_when is port( a, b : in std_logic; s : in std_logic; y : out std_logic); end mux 21_when; architecture a of mux 21_when is begin y <= a when (s='0') else b; end a; 마지막 조건은 else 로 처리해야 함 회로보다 는 동작 에 관심.
Behavioral - Signal Assignment, Selected library ieee; use ieee. std_logic_1164. all; entity mux 21_with is port( a, b: in std_logic; s : in std_logic; y : out std_logic); end mux 21_with; architecture a of mux 21_with is BEGIN WITH s SELECT y <= a WHEN ‘ 0’, b WHEN others; END a; 마지막 조 건은 else 로 처리해 야함
Behavioral – Sequential Statement (IF) library ieee; use ieee. std_logic_1164. all; entity mux 21_if_proc is port( a, b : in std_logic; s : in std_logic; y : out std_logic); end mux 21_if_proc; architecture proc of mux 21_if_proc is begin process(a, b, s) begin if( s='0') then y<=a; else y<=b; end if; end process; end proc; a, b, s 에 변화생길 때 실행 마지막 조건은 else로 처리해야 함.
Behavioral – Process Statement (case) library ieee; use ieee. std_logic_1164. all; entity mux 21_case_proc is port( a, b : in std_logic; s : in std_logic; y : out std_logic); end mux 21_case_proc; architecture proc of mux 21_case_proc is begin process(a, b, s) begin case s is when '0' => y<= a; when others => y<= b; end case; end process; end proc; 마지막 조건은 others로 처리 해야 함.
Behavioral – Signal vs. Variable 1. library ieee; use ieee. std_logic_1164. all; 2. use ieee. std_logic_1164. all; entity andor_2 is 3. entity port( a, b, c : in std_logic; andor_2 is 4. port( a, b, c : in std_logic; 5. y : out std_logic); 6. end andor_2; 7. architecture is 8. signal 선언되는 위치차이 a of andor_2 process(a, b, c, t) 11. begin t<=a 3 and 13. y<=t or c; end process; a; Begin begin t : =a and b; 1 y<=t or c; 1 12. 14. architecture a of andor_2 is variablel t : std_logic; 2 10. b; Sensitivit y List차 이 process(a, b, c) t : std_logic; 9. Begin 15. end y : out std_logic); Signal t는 Process문 이 끝나는 순 간에 일괄적 으로 값이 할 당. end process; end a; 2 Variable은 대입 즉시 값 할당. 55
참고문헌 1. 2. 3. 4. 5. 6. PERRY, VHDL 4/E : PROGRAMMING BY EXAMPLE. FLOYD, DIGITAL FUNDAMENTALS WITH VHDL. ARMSTRONG, GRAY, VHDL DESIGN REPRESENTATION & SYNTHESIS. SKHILL, VHDL FOR PROGRAMMABLE LOGIC. PELLERIN, VHDL MADE EASY. LEE, VHDL CODING & LOGIC SYNTHESIS WITH SYNOPSYS.
- Slides: 56