7 Segment Displays VHDL Tutorial R E Haskell

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7 -Segment Displays VHDL Tutorial R. E. Haskell and D. M. Hanna T 4:

7 -Segment Displays VHDL Tutorial R. E. Haskell and D. M. Hanna T 4: Xilinx Logi. BLOX

7 -Segment Decoder a-g LOW to turn on segment

7 -Segment Decoder a-g LOW to turn on segment

7 -Segment Decoder library IEEE; use IEEE. std_logic_1164. all; entity seg 7 dec is

7 -Segment Decoder library IEEE; use IEEE. std_logic_1164. all; entity seg 7 dec is port (q: in STD_LOGIC_VECTOR(3 downto 0); Ato. G: out STD_LOGIC_VECTOR(6 downto 0)); end seg 7 dec;

architecture seg 7 dec_arch of seg 7 dec is begin process(q) begin case q

architecture seg 7 dec_arch of seg 7 dec is begin process(q) begin case q is when "0000" => Ato. G <= "0000001"; when "0001" => Ato. G <= "1001111"; when "0010" => Ato. G <= "0010010"; when "0011" => Ato. G <= "0000110"; when "0100" => Ato. G <= "1001100"; when "0101" => Ato. G <= "0100100"; when "0110" => Ato. G <= "0100000"; when "0111" => Ato. G <= "0001101"; when "1000" => Ato. G <= "0000000"; when "1001" => Ato. G <= "0000100"; when "1010" => Ato. G <= "0001000"; when "1011" => Ato. G <= "1100000"; when "1100" => Ato. G <= "0110001"; when "1101" => Ato. G <= "1000010"; when "1110" => Ato. G <= "0110000"; when others => Ato. G <= "0111000"; end case; end process; end seg 7 dec_arch;

Digilab Board dig 4 dig 3 dig 2 dig 1

Digilab Board dig 4 dig 3 dig 2 dig 1

Digilab Board – Common Anodes Pins A 4 A 3 A 2 A 1

Digilab Board – Common Anodes Pins A 4 A 3 A 2 A 1 CA CB CC CD CE CF CG

Multiplex displays 1 0 0 0 0 1 1 0

Multiplex displays 1 0 0 0 0 1 1 0

Multiplex displays 0 1 0 0 0 1 1

Multiplex displays 0 1 0 0 0 1 1

Multiplex displays 0 0 1 1 0 0

Multiplex displays 0 0 1 1 0 0

Multiplex displays 0 0 0 1 1 1 0 0 0

Multiplex displays 0 0 0 1 1 1 0 0 0

Multiplex displays dig 7 seg dig 1(3: 0) dig 2(3: 0) mux 4 dig

Multiplex displays dig 7 seg dig 1(3: 0) dig 2(3: 0) mux 4 dig 3(3: 0) y 1(3: 0) seg 7 dec Ato. G(6: 0) dig 4(3: 0) Asel(1: 0) clk anode(3: 0) ctr 2 bit Acode Aen(3: 0) A(4: 1)

dig 7 seg entity dig 7 seg is port ( anode: in STD_LOGIC_VECTOR (3

dig 7 seg entity dig 7 seg is port ( anode: in STD_LOGIC_VECTOR (3 downto 0); dig 1: in STD_LOGIC_VECTOR (3 downto 0); dig 2: in STD_LOGIC_VECTOR (3 downto 0); dig 3: in STD_LOGIC_VECTOR (3 downto 0); dig 4: in STD_LOGIC_VECTOR (3 downto 0); clk: in STD_LOGIC; Ato. G: out STD_LOGIC_VECTOR (6 downto 0); A: out STD_LOGIC_VECTOR (4 downto 1) ); end dig 7 seg;

dig 7 seg architecture dig 7 seg_arch of dig 7 seg is signal y

dig 7 seg architecture dig 7 seg_arch of dig 7 seg is signal y 1: STD_LOGIC_VECTOR (3 downto 0); signal sel 2: STD_LOGIC_VECTOR (1 downto 0); begin u 0: ctr 2 bit port map (CLOCK => clk, Q_OUT => sel 2); u 1: mux 4 g port map (a => dig 1, b => dig 2, c => dig 3, d => dig 4, sel => sel 2, y => y 1); u 2: seg 7 dec port map (q => y 1, Ato. G => Ato. G); u 3: Acode port map (Aen => anode, Asel => sel 2, A => A); end dig 7 seg_arch;

ctr 2 bit -- A 2 -bit up-counter library IEEE; use IEEE. std_logic_1164. all;

ctr 2 bit -- A 2 -bit up-counter library IEEE; use IEEE. std_logic_1164. all; use IEEE. std_logic_unsigned. all; entity ctr 2 bit is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (1 downto 0) ); end ctr 2 bit;

ctr 2 bit (cont. ) architecture ctr 2 bit_arch of ctr 2 bit is

ctr 2 bit (cont. ) architecture ctr 2 bit_arch of ctr 2 bit is begin process (clk, clr) variable COUNT: STD_LOGIC_VECTOR (1 downto 0); begin if clr = '1' then q <= "00"; elsif clk'event and clk='1' then COUNT : = COUNT + 1; q <= COUNT; end if; end process; end ctr 2 bit_arch;

Acode library IEEE; use IEEE. std_logic_1164. all; entity Acode is port ( Aen: in

Acode library IEEE; use IEEE. std_logic_1164. all; entity Acode is port ( Aen: in STD_LOGIC_VECTOR (3 downto 0); Asel: in STD_LOGIC_VECTOR (1 downto 0); A: out STD_LOGIC_VECTOR (3 downto 0) ); end Acode;

architecture Acode_arch of Acode is begin process(Aen, Asel) begin A <= "0000"; case Asel

architecture Acode_arch of Acode is begin process(Aen, Asel) begin A <= "0000"; case Asel is when "00" => if Aen(0) = '1' then A <= "0001"; end if; when "01" => if Aen(1) = '1' then A <= "0010"; end if; when "10" => if Aen(2) = '1' then A <= "0100"; end if; when others => if Aen(3) = '1' then A <= "1000"; end if; end case; end process; end Acode_arch;

step_display

step_display

step_display library IEEE; use IEEE. std_logic_1164. all; entity step_display is port ( dig 1,

step_display library IEEE; use IEEE. std_logic_1164. all; entity step_display is port ( dig 1, dig 2: in STD_LOGIC_VECTOR (3 downto 0); dig 3, dig 4: in STD_LOGIC_VECTOR (3 downto 0); step: in STD_LOGIC; clr: in STD_LOGIC; clkout: out STD_LOGIC; clrout: out STD_LOGIC; Ato. G: out STD_LOGIC_VECTOR (6 downto 0); A: out STD_LOGIC_VECTOR (4 downto 1) ); end step_display;

architecture step_display_arch of step_display is signal anode: STD_LOGIC_VECTOR (3 downto 0); signal clk 4:

architecture step_display_arch of step_display is signal anode: STD_LOGIC_VECTOR (3 downto 0); signal clk 4: STD_LOGIC; begin anode <= "1111"; clrout <= clr; u 1: dig 7 seg port map (anode => anode, dig 4 => dig 4, dig 3 => dig 3, dig 2 => dig 2, dig 1 => dig 1, clk => clk 4, Ato. G => Ato. G, A => A); u 2: osc_4 k port map (clk => clk 4); u 3: debounce port map (inp => step, clk => clk 4, clr => clr, outp => clkout); end step_display_arch;

T 4 Lab Exercise

T 4 Lab Exercise

T 4 main library IEEE; use IEEE. std_logic_1164. all; entity T 4 main is

T 4 main library IEEE; use IEEE. std_logic_1164. all; entity T 4 main is port ( SW: in STD_LOGIC_VECTOR (1 to 8); BTN: in STD_LOGIC_VECTOR (1 to 4); LD: out STD_LOGIC_VECTOR (1 to 8); Ato. G: out STD_LOGIC_VECTOR (6 downto 0); A: out STD_LOGIC_VECTOR (3 downto 0) ); end T 4 main;

architecture T 4 main_arch of T 4 main is signal tin, T, N, y:

architecture T 4 main_arch of T 4 main is signal tin, T, N, y: std_logic_vector(7 downto 0); signal clr, clk: std_logic; begin U 0: mux 2 port map (a =>y, b => SW, sel => SW(1), y => tin); Treg: reg port map (d => tin, load => SW(2), clr => clr, clk =>clk, q => T); Nreg: reg port map (d => T, load => SW(3), clr => clr, clk =>clk, q => N); U 1: alu port map (a => T, b => N, sel => SW(4 to 5), y => y); U 2: step_display port map (dig 1 => T(3 downto 0), dig 2 => T(7 downto 4), dig 3 => N(3 downto 0), dig 4 => N(7 downto 4), step => BTN(4), clr => BTN(1), clkout => clk, clrout => clr, A => A, Ato. G => Ato. G); LD <= SW; end T 4 main_arch;