Multiplication Lecture L 6 2 VHDL Multiply Operator

Multiplication Lecture L 6. 2 VHDL Multiply Operator (*)

Multiplication 13 x 11 13 13 143 = 8 Fh 1101 x 1011 1101 100111 0000 100111 1101 10001111

Multiplication 1101 x 1011 1101 100111 0000 100111 1101 10001111 1101 00001011 01101101 adsh 1101 10011110 adsh 1001111 sh 1101 10001111 adsh

std_logic_arith. vhd library IEEE; use IEEE. std_logic_1164. all; package std_logic_arith is type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC; subtype SMALL_INT is INTEGER range 0 to 1; function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; R: SIGNED) return SIGNED; R: UNSIGNED) return SIGNED; UNSIGNED; R: SIGNED) return SIGNED; function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;

function constant variable mult(A, B: UNSIGNED) return UNSIGNED is msb: integer: =A'length+B'length-1; BA: UNSIGNED(msb downto 0); PA: UNSIGNED(msb downto 0); begin if (A(A'left) = 'X' or B(B'left) = 'X') then PA : = (others => 'X'); return(PA); end if; PA : = (others => '0'); BA : = CONV_UNSIGNED(B, (A'length+B'length)); for i in 0 to A'length-1 loop if A(i) = '1' then PA : = PA+BA; end if; for j in msb downto 1 loop BA(j): =BA(j-1); end loop; BA(0) : = '0'; end loop; return(PA); end; 1101 x 1011 1101 100111 0000 100111 1101 10001111

function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is begin return end; mult(CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length));

std_logic_unsigned. vhd library IEEE; use IEEE. std_logic_1164. all; use IEEE. std_logic_arith. all; package STD_LOGIC_UNSIGNED is function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;

std_logic_unsigned. vhd (cont. ) library IEEE; use IEEE. std_logic_1164. all; use IEEE. std_logic_arith. all; package body STD_LOGIC_UNSIGNED is function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is constant length: INTEGER : = maximum(L'length, R'length); variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0); begin result : = UNSIGNED(L) * UNSIGNED(R); return end; std_logic_vector(result);

Testing the * operator Use BTN 4 to load SW into Ra and Rb and then display product in Rp Control signals: aload bload pload dmsel m 2 sel(1: 0)

Three consecutive pushings of BTN 4 Control signals: aload bload pload dmsel m 2 sel(1: 0)

VHDL Canonical Sequential Network s(t+1) next state State Register x(t) present input Combinational Network init process(clk, init) clk process(present_state, x) s(t) present state present z(t) output

-- Title: Mult Control Unit library IEEE; use IEEE. std_logic_1164. all; use IEEE. std_logic_unsigned. all; entity mult_control is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; BTN 4: in STD_LOGIC; m 2 sel: out STD_LOGIC_VECTOR (1 downto 0); aload, bload, dmsel: out STD_LOGIC; pload: out STD_LOGIC ); end mult_control;

mult_control. vhd architecture mult_control_arch of mult_control is type state_type is (s. A, s. B, s. C, s. D, s. E, s. F); signal current_state, next_state: state_type; begin C 1: process(current_state, BTN 4) begin -- Initialize all outputs pload <= '0'; dmsel aload bload m 2 sel <= <= '0'; "00";

case current_state is when s. A => --wait for BTN 4 up if BTN 4 = '1' then next_state <= s. A; m 2 sel <= "11"; else next_state <= s. B; end if; when s. B => if BTN 4 = '1' then next_state <= s. C; aload <= '1'; m 2 sel <= "00"; else next_state <= s. B; m 2 sel <= "11"; end if; --wait for BTN 4 down -- A <- SW

when s. C => --wait for BTN 4 up if BTN 4 = '1' then next_state <= s. C; m 2 sel <= "00"; else next_state <= s. D; end if; when s. D => if BTN 4 = '1' then next_state <= s. E; dmsel <= '1'; bload <= '1'; m 2 sel <= "01"; else next_state <= s. D; m 2 sel <= "00"; end if; --wait for BTN 4 down -- B <- SW

when s. E => --wait for BTN 4 up if BTN 4 = '1' then next_state <= s. E; m 2 sel <= "01"; else next_state <= s. F; end if; when s. F => if BTN 4 = '1' then next_state <= s. A; pload <= '1'; m 2 sel <= "11"; else next_state <= s. F; m 2 sel <= "01"; end if; end case; end process C 1; --wait for BTN 4 down

statereg: process(clk, clr) -- the state register begin if clr = '1' then current_state <= s. A; elsif (clk'event and clk = '1') then current_state <= next_state; end if; end process statereg; end mult_control_arch;

-- Title: Multiply Test library IEEE; mult. vhd use IEEE. STD_LOGIC_1164. all; use IEEE. std_logic_unsigned. all; use work. mult_components. all; entity mult is port( mclk : in STD_LOGIC; bn : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(1 to 8); BTN 4: in STD_LOGIC; led: out std_logic; ldg : out STD_LOGIC; LD : out STD_LOGIC_VECTOR(1 to 8); Ato. G : out STD_LOGIC_VECTOR(6 downto 0); A : out STD_LOGIC_VECTOR(3 downto 0) ); end mult;

architecture mult_arch of mult is signal r, p, pout, x, b 16, a 16: std_logic_vector(15 downto 0); as, bs, ain, bin: std_logic_vector(7 downto 0); clr, clk, cclk, bnbuf: std_logic; clkdiv: std_logic_vector(26 downto 0); signal aload, bload, pload, dmsel: STD_LOGIC; signal m 2 sel: STD_LOGIC_VECTOR (1 downto 0); constant bus_width 8: positive : = 8; constant bus_width 16: positive : = 16;

begin U 00: IBUFG port map (I => bn, O => bnbuf); led <= bnbuf; ldg <= '1'; -- enable 74 HC 373 latch clr <= bnbuf; -- Divide the master clock (50 Mhz) process (mclk) begin if mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; end process; clk <= clkdiv(0); cclk <= clkdiv(17); -- 25 MHz -- 190 Hz

a 16 <= "0000" & as; b 16 <= "0000" & bs; p <= as * bs; U 1: dmux 2 g generic map(width => bus_width 8) port map (y => SW, a => ain, b => bin, sel => dmsel); U 2 a: reg generic map(width => bus_width 8) port map (d => ain, load => aload, clr => clr, clk =>clk, q => as); U 3 b: reg generic map(width => bus_width 8) port map (d => bin, load => bload, clr => clr, clk =>clk, q => bs); U 4 p: reg generic map(width => bus_width 16) port map (d => p, load => pload, clr => clr, clk =>clk, q => pout);

U 5: mux 4 g generic map(width => bus_width 16) port map (a => a 16, b => b 16, c => pout, d => pout, sel => m 2 sel, y => r); U 6: binbcd port map (B => r, P => x); U 7: x 7 seg port map (x => x, cclk => cclk, clr => clr, Ato. G => Ato. G, A => A); U 8: mult_control port map (clr => clr, clk => clk, BTN 4 => BTN 4, m 2 sel => m 2 sel, aload => aload, bload => bload, dmsel => dmsel, pload => pload); LD <= SW; end mult_arch;