STATIC TIMING ANALYSIS 1 Introduction Effective methodology for

STATIC TIMING ANALYSIS 1

Introduction Ø Effective methodology for verifying the timing characteristics of a design without the use of test vectors Ø Conventional verification techniques are inadequate for complex designs Ø Simulation time using conventional simulators Ø Thousands of test vectors are required to test all timing paths using logic simulation Ø Increasing design complexity & smaller process technologies Ø Increases the number of iterations for STA 2

Simulation vs. Static timing True timing paths False timing paths Timing Simulation (adding vectors) 0% Static timing analysis (eliminating false paths) 100% STA approach typically takes a fraction of the time it takes to run logic simulation on a large design and guarantees 100% coverage of all true timing paths in the design without having to generate test vectors 3

OVERVIEW Previous Verification Flow 4

OVERVIEW • Requires extensive vector creation • Valid for FPGAs and smaller ASICs • Falls apart on multi-million gate ASICs 5

What is Static Timing Analysis? Static Timing Analysis is a method for determining if a circuit meets timing constraints without having to simulate ØMuch faster than timing-driven, gate-level simulation ØProper circuit functionality is not checked ØVector generation NOT required 6

STA in ASIC Design Flow – Pre layout Logic Synthesis Constraints (clocks, input drive, output load) Design For test Floor planning Static Timing Analysis (estimated parasitics) 7

STA in ASIC Design Flow – Post Layout Floor planning Constraints (clocks, input drive, output load) Static Timing Analysis (estimated parasitics) Clock Tree Synthesis Place and Route Parasitic Extraction Static Timing Analysis (extracted parasitics) SDF (extracted parasitics) 8

2 Types of Timing Verification Dynamic Timing Simulation Advantages ØCan be very accurate (spice-level) Disadvantages ØAnalysis quality depends on stimulus vectors ØNon-exhaustive, slow Examples: VCS, Spice, ACE 9

2 Types of Timing Verification Static Timing Analysis (STA) Advantages ØFast, exhaustive ØBetter analysis checks against timing requirements Disadvantage ØLess accurate ØMust define timing requirements/exceptions ØDifficulty handling asynchronous designs, false paths 10

Three Steps in Static Timing Analysis Ø Circuit is broken down into sets of timing paths Ø Delay of each path is calculated Ø Path delays are checked to see if timing constraints have been met 11

What is a Timing Path? A Timing Path is a point-to-point path in a design which can propagate data from one flip-flop to another v. Each path has a start point and an endpoint ØStart point: ØInput ports Clock pins of flip-flops ØEndpoints: ØOutput ports Data input pins of flip-flops 12

Organizing Timing Paths Into Groups Timing paths are grouped into path groups by the clocks controlling their endpoints Synthesis tools like Prime. Time and Design Compiler organize timing reports by path groups 13

Net and Cell Timing Arcs The actual path delay is the sum of net and cell delays along the timing path 14

Net and Cell Delay “Net Delay” refers to the total time needed to charge or discharge all of the parasitics of a given net ØTotal net parasitics are affected by Ønet length Ønet fanout ØNet delay and parasitics are typically ØBack-Annotated (Post-Layout) from data obtained from an extraction tool ØEstimated (Pre-Layout) 15

Cell Delay In ASICs, the delay of a cell is affected by: ØThe input transition time (or slew rate) ØThe total load “seen” by the output transistors Net capacitance and “downstream” pin capacitances ØThese will affect how quickly the input and output transistors can “switch” ØInherent transistor delays and “internal” net delays 16

Clocked Storage Elements Transparent Latch, Level Sensitive – data passes through when clock high, latched when clock low D-Type Register or Flip-Flop, Edge-Triggered – data captured on rising edge of clock, held for rest of cycle 17

Flip-Flops 18

Basic terminologies Ø Ø Ø Ø Pulse Width Setup & Hold times Signal slew Clock latency Clock Skew Input arrival time Output required time Slack and Critical path Ø Recovery & Removal times Ø False paths Ø Multi-cycle paths 19

Pulse Width Ø Pulse width Ø It is the time between the active and inactive states of the same signal 20

Setup and Hold time Ø Setup time Ø For an edge triggered sequential element, the setup time is the time interval before the active clock edge during which the data should remain unchanged Ø Hold time Ø Time interval after the active clock edge during which the data should remain unchanged Both the above 2 timing violations can occur in a design when clock path delay > data path delay 21

Signal Slew Ø Signal (Clock/Data) slew Ø Amount of time it takes for a signal transition to occur Ø Accounts for uncertainty in Rise and fall times of the signal Ø Slew rate is measured in volts/sec 22

Clock Latency Ø Difference between the reference (source) clock slew to the clock tree endpoint signal slew values Ø Rise latency and fall latency are specified INV INV Rise=7 Fall=4 CLK INV Rise=7 Fall=4 BUF Rise=7 Fall=4 CLKA INV Rise=7 Fall=4 CLKB CLKC BUF Rise=7 Fall=4 23

Clock Latency 24

Clock Skew Ø Clock Skew is a measure of the difference in latency between any two leaf pins in a clock tree. Ø between CLKA and CLKB rise = 22 -8 = 14 fall = 22 -14 = 8 Ø between CLKB and CLKC rise = 8 -7 = 1 fall = 14 -4 = 10 Ø between CLKA and CLKC rise = 22 -7 = 15 fall = 22 -4 = 18 It is also defined as the difference in time that a single clock signal takes to reach two different registers 25

Input Arrival time Ø An arrival time defines the time interval during which a data signal can arrive at an input pin in relation to the nearest edge of the clock signal that triggers the data transition 26

Output required time Ø Specifies the data required time on output ports. 27

Slack and Critical path Ø Slack Ø It is the difference between the required (constraint) time and the arrival time (inputs and delays). Ø Negative slack indicates that constraints have not been met, while positive slack indicates that constraints have been met. Ø Slack analysis is used to identify timing critical paths in a design by the static timing analysis tool Ø Critical path Ø Any logical path in the design that violates the timing constraints Ø Path with a negative slack 28

Slack Analysis – Data Path types 29

Slack analysis – data path types Ø Primary input-to-register paths Ø Delays off-chip + Combinational logic delays up to the first sequential device. Ø Register-to-primary output paths Ø Start at a sequential device Ø CLK-to-Q transition delay + the combinational logic delay + external delay requirements Ø Register-to-register paths Ø Delay and timing constraint (Setup and Hold) times between sequential devices for synchronous clocks + source and destination clock propagation times. Ø Primary input-to-primary output paths Ø Delays off-chip + combinational logic delays + external delay requirements. 30

Hold Slack calculation Ø Actual data arrival time definition Data Input Arrival Timemin + Data path delaymin If the data path starts in a primary input, Data Input arrivalmin = Input arrival timemin If the data path starts at a register, (Source Clock Edgemin + Source Clock Path Delaymin) = Data Input Arrivalmin Ø Required Stability time definition (Destination Clock Edgemax + Destination Clock Path Delaymax) + Hold = Required Stability Timemax Ø Hold Slack definition Actual Data Arrivalmin - Required Stability Timemax 31

Calculate the hold slack Source Clock signal timing parameters: Min Edge = 8. 002 ns Min clock path delay = 0. 002 ns Min Data path delay = 0. 802 ns Hold time constraint = 1. 046 ns Destination Clock signal timing parameters: Max Edge = 2. 020 ns Max clock path delay = 0. 500 ns 32

Hold slack calculation 33

Setup Slack calculation Ø Actual data arrival time definition Data Input Arrival Timemax + Data path delaymax If the data path starts in a primary input, Data Input arrivalmax = Input arrival timemax If the data path starts at a register, (Source Clock Edgemax + Source Clock Path Delaymax) = Data Input Arrivalmax Ø Required Stability time definition (Destination Clock Edgemin + Destination Clock Path Delaymin) Setup = Required Stability Timemin Ø Setup slack definition Required Stability Timemin - Actual Data Arrivalmax 34

Calculate the setup slack Source Clock signal timing parameters: Max Edge = 2. 002 ns Max clock path delay = 0. 002 ns Min Data path delay = 13. 002 ns Setup time constraint = 0. 046 ns Destination Clock signal timing parameters: Min Edge = 20. 02 ns Min clock path delay = 0. 500 ns 35

Setup slack calculation 36

Recovery and Removal time Ø Recovery time Like setup time for asynchronous port (set, reset) Ø Removal time Like hold time for asynchronous port (set, reset) Ø Recovery time It is the time available between the asynchronous signal going inactive to the active clock edge Ø Removal time It is the time between active clock edge and asynchronous signal going inactive 37

False Paths Ø False paths Ø Paths that physically exist in a design but are not logic/functional paths Ø These paths never get sensitized under any input conditions Mux 1 A Mux 2 C B 1 C 2 OUT B 2 B S 38

Multi-cycle paths Ø Data Paths that require more than one clock period for execution 2 clock period delay 39

Sequential Circuit Timing Objectives This section covers several timing considerations encountered in the design of synchronous sequential circuits. It has the following objectives: Ø Define the following global timing parameters and show they can be derived from the basic timing parameters of flip-flops and gates. • Maximum Clock Frequency • Maximum allowable clock skew • Global Setup and Hold Times Ø Discuss ways to control the loading of data into registers and show why gating the clock signal to do this is a poor design practice. 40

Maximum Clock Frequency Ø The clock frequency for a synchronous sequential circuit is limited by the timing parameters of its flip-flops and gates. This limit is called the maximum clock frequency for the circuit. The minimum clock period is the reciprocal of this frequency. Ø Relevant timing parameters v Gates: • Propagation delays: min t. PLH, min t. PHL, max t. PLH, max t. PHL v Flip-Flops: • • • Propagation delays: min t. PLH, min t. PHL, max t. PLH, max t. PHL Setup time: tsu Hold time: th 41

Ø Example TW ≥ max t. PFF + tsu For the 7474, max t. PLH = 25 ns, max t. PHL = 40 ns, tsu = 20 ns TW ≥ max (max t. PLH + tsu, max t. PHL + tsu) TW ≥ max (25+20, 40+20) = 60 42

Ø Example TW ≥ max t. PFF + max t. PINV + tsu 43

Ø Example TW ≥ max t. PFF + max t. PMUX + tsu 44

Ø Example Paths from Q 1 to Q 1: None Paths from Q 1 to Q 2: TW ≥ max t. PDFF +t. JKsu = 20 +10 = 30 ns TW ≥ max t. PDFF + max t. AND + t. JKsu = 20 + 12 + 10 = 42 ns Paths from Q 2 to Q 1: TW ≥ max t. PJKFF + t. OR + TDsu = 25 + 10 + 5 = 40 ns Paths from Q 2 to Q 2: TW ≥ max t. PJKFF + max t. AND + t. JKsu = 25 + 12 + 10 = 47 ns TW ≥ 47 ns 45

Clock Skew Ø If a clock edge does not arrive at different flip-flops at exactly the same time, then the clock is said to be skewed between these flip-flops. The difference between the times of arrival at the flip-flops is said to be the amount of clock skew. Ø Clock skew is due to different delays on different paths from the clock generator to the various flip-flops. • • • Different length wires (wires have delay) Gates (buffers) on the paths Flip-Flops that clock on different edges (need to invert clock for some flip-flops) • Gating the clock to control loading of registers (a very bad idea) 46

• Example (Effect of clock skew on clock rate) Ø Clock C 2 skewed after C 1 TW ≥ max TPFF + max t. OR + tsu (if clock not skewed, i. e. , t. INV = 0) TW ≥ max TPFF + max t. OR + tsu - min t. INV (if clock skewed, i. e. , t. INV > 0) 47

Ø Clock C 1 skewed after C 2 TW ≥ max TPFF + max t. OR + tsu (if clock not skewed, i. e. , t. INV = 0) TW ≥ max TPFF + max t. OR + tsu + max t. INV (if clock skewed, i. e. , t. INV > 0) 48

Ø Summary of maximum clock frequency calculations C 2 skewed after C 1: TW ≥ max TPFF + max t. NET + tsu - min t. INV C 2 skewed before C 1: TW ≥ max TPFF + max t. NET + tsu + max t. INV 49

Maximum Allowable Clock Skew Ø How much skew between C 1 and C 2 can be tolerated in the following circuit? – Case 1: C 2 delayed after C 1 t. PFF > th + t. SK < min t. PFF - th 50

Ø Case 2: C 1 delayed from C 2 51

Ø How does additional delay between the flip-flops affect the skew calculations? t. SK ≤ min t. PFF - th tsk ≤ min t. PFF + min t. MUX - th 52

Ø Summary of allowable clock skew calculations t. SK + th ≤ t. PFF + t. NET t. SK ≤ min t. PFF + min t. NET - th 53

Ø Example: What is the minimum clock period for the following circuit under the assumption that the clock C 2 is skewed after C 1 (i. e. , C 2 is delayed from C 1)? 54

Ø First calculate the maximum allowable clock skew. t. SK < min t. PFF + min t. N 1 - th Ø Next calculate the minimum clock period due to the path from Q 1 to D 2. TW > max t. PFF + max t. N 1 + tsu - min t. SK Ø Finally calculate the minimum clock period due to the path from Q 2 to D 1 TW > max t. PFF + max t. N 1 + tsu + max t. SK TW > max t. PFF + max t. N 2 + tsu + (min t. PFF + min t. N 1 - th) TW > max t. PFF + min t. PFF + max t. N 2 + min t. N 1 + tsu - th 55

Global Setup Time, Hold Time and Propagation Delay Ø Global setup and hold times (data delayed) TSU = tsu + max t. NET TH = th - min t. NET 56

Ø Global setup & hold time (clock delayed) TSU = tsu - min t. C TH = th + max t. C 57

Ø Global setup & hold time (data & clock delayed) TSU = + max =-0987654321 - min. TH = th - min t. NET + max t. C 58

Ø Global propagation delay TP = t. C + t. FF + t. NET 59

Ø Summary of global timing parameters TSU = tsu + max t. PN - min t. PC ≤ tsu + max t. PN TH = th + max t. PC - min t. PN ≤ th + max t. PC TP = t. PFF + t. PN + t. PC 60

Ø Example v Find TSU and TH for input signal LD relative to CLK. TSU = tsu +max t. NET - min t. C = tsu + max t. INV + max t. NAND - min t. INV TH = th - min t. NET + max t. C = th - min t. NAND + max TINV 61

Register load control (gating the clock • A very bad way to add a load control signal LD to a register that does not have one is shown below • The reason this is such a bad idea is illustrated by the following timing diagram. • The flip-flop sees two rising edges and will trigger twice. The only one we want is the second one. 62

Ø If LD was constrained to only change when the clock was low, then the only problem would be the clock skew. 63

Ø If gating the clock is the only way to control the loading of registers, then use the following approach: Ø There is still clock skew, but at least we only have one triggering edge. 64

Ø The best way to add a LD control signal is as follows: 65

Tips & Tricks Ø Use timing diagrams to determine the timing properties of sequential circuits Ø Using typical timing values from the data sheet (use only max and/or min values) Ø Gating the clock 66

Detecting timing violations – CASE 1 (a) Hold time for clocks is 1. 5 ns Determine if there any timing violations in this design DFF 1 Delay (min) = 5 ns DFF 2 Data clk 20 Mhtzref clk 10 Mhtz 67

Detecting timing violations – CASE 2 (a) Hold time for clocks is 1. 5 ns (b) Clock skew of 3. 72 ns between clk 20 mref and clk 10 mz Determine if there any timing violations in this design DFF 1 Delay (min) = 5 ns DFF 2 Data clk 20 Mhtzref clk 10 Mhtz 68

Detecting timing violations – CASE 3 (a) Hold time for clocks is 1. 5 ns (b) Clock skew of 3. 72 ns between clk 20 mref and clk 10 mz DFF 1 Delay (min) = 5 ns DFF 2 Data clk 20 Mhtzref clk 10 Mhtz 69

Detecting timing violations – CASE 4 Consider (a) Clock skew of 3. 72 ns between clk 20 mref and clk 10 mz (b) Clock network delays DFF 1 Delay (min) = 5 ns DFF 2 Data clk 20 Mhtzref Propagation delay = 4 ns (thru clock tree buffers) clk 10 Mhtz Propagation delay = 2 ns (thru clock tree buffers) 70

Thank you 71