Chapter 3 Digital Logic Structures Copyright The Mc

Chapter 3 Digital Logic Structures

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Transistor: Building Block of Computers Microprocessors contain millions of transistors • Intel Pentium II: 7 million • Compaq Alpha 21264: 15 million • Intel Pentium III: 28 million Logically, each transistor acts as a switch Combined to implement logic functions • AND, OR, NOT Combined to build higher-level structures • Adder, multiplexor, decoder, register, … Combined to build processor • LC-2 Wael Qassas/AABU 2

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Simple Switch Circuit Switch open: • No current through circuit • Light is off • Vout is + 5 V Switch closed: • • Short circuit across switch Current flows Light is on Vout is 0 V Switch-based circuits can easily represent two states: on/off, open/closed, voltage/no voltage. Wael Qassas/AABU 3

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. LOGICAL AND: Wael Qassas/AABU 4

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. N-type MOS Transistor MOS = Metal Oxide Semiconductor • two types: N-type and P-type N-type • when Gate has positive voltage, short circuit between #1 and #2 (switch closed) • when Gate has zero voltage, open circuit between #1 and #2 (switch open) Gate = 1 Gate = 0 Terminal #2 must be connected to GND (0 V). Wael Qassas/AABU 5

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. P-type MOS Transistor P-type is complementary to N-type • when Gate has positive voltage, open circuit between #1 and #2 (switch open) • when Gate has zero voltage, short circuit between #1 and #2 (switch closed) Gate = 1 Gate = 0 Terminal #1 must be connected to +2. 9 V. Wael Qassas/AABU 6

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Logic Gates Use switch behavior of MOS transistors to implement logical functions: AND, OR, NOT. Digital symbols: • recall that we assign a range of analog voltages to each digital (logic) symbol • assignment of voltage ranges depends on electrical properties of transistors being used Ø typical values for "1": +5 V, +3. 3 V, +2. 9 V Ø from now on we'll use +5 V Wael Qassas/AABU 7

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. CMOS Circuit Complementary MOS Uses both N-type and P-type MOS transistors • P-type Ø Attached to + voltage Ø Pulls output voltage UP when input is zero • N-type Ø Attached to GND Ø Pulls output voltage DOWN when input is one For all inputs, make sure that output is either connected to GND or to +, but not both! Wael Qassas/AABU 8

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Inverter (NOT Gate) Truth table In Out 0 V 2. 9 V 0 1 1 0 2. 9 V 0 V Wael Qassas/AABU 9

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. NOR Gate Note: Serial structure on top, parallel on bottom. A B C 0 0 1 0 1 0 0 1 1 0 Wael Qassas/AABU 10

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. OR Gate A B C 0 0 1 1 1 0 1 1 Add inverter to NOR. Wael Qassas/AABU 11

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. NAND Gate (AND-NOT) Note: Parallel structure on top, serial on bottom. A B C 0 0 1 1 1 0 Wael Qassas/AABU 12

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. AND Gate A B C 0 0 1 1 1 Add inverter to NAND. Wael Qassas/AABU 13

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Basic Logic Gates Wael Qassas/AABU 14

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Fundamental Properties of boolean algebra: Commutative: Ø X+Y=Y+X Ø X. Y= Y. X Associative: Ø ( X + Y) + Z = X + (Y + Z) Ø ( X. Y). Z = X. (Y. Z) Distributive: Ø X. (Y + Z) = (X. Y) + (X. Z) Ø X + (Y. Z) = (X + Y). (X + Z) Identity: ØX + 0 = X ØX. 1 = X Complement: Ø X +X’ = 1 Ø X. X’ = 0 Wael Qassas/AABU 15

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. X+1 X+0 X. X X. 1 X. 0 X+XY Wael Qassas/AABU 16

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. More than 2 Inputs? AND/OR can take any number of inputs. • AND = 1 if all inputs are 1. • OR = 1 if any input is 1. • Similar for NAND/NOR. Can implement with multiple two-input gates, or with single CMOS circuit. Wael Qassas/AABU 17

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Practice Implement a 3 -input NOR gate with CMOS. Wael Qassas/AABU 18

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Logical Completeness Can implement ANY truth table with AND, OR, NOT. A B C D 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1. AND combinations that yield a "1" in the truth table. 2. OR the results of the AND gates. Wael Qassas/AABU 19

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Practice Implement the following truth table. A B C 0 0 1 1 1 0 A B C Wael Qassas/AABU 20

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Another example: We want to build a circuit that has 3 binary inputs. This CKT is On if the inputs are X’Y’Z or X’YZ’. X Y Z Output 0 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 0 X Y Z Output Wael Qassas/AABU 21

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. XOR gate: A XOR B= A. B’+A’. B A+B A B A+B 0 0 1 1 1 0 A B A. B’+A’. B Wael Qassas/AABU 22

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. De. Morgan's Law Converting AND to OR (with some help from NOT) Consider the following gate: A B 0 0 1 1 1 0 0 1 1 1 0 0 0 1 To convert AND to OR (or vice versa), invert inputs and output. Same as A+B Wael Qassas/AABU 23

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. De. Morgan Law: ØA+B= (A’. B’)’ A B A’ B’ A’. B’ (A’. B’)’ 0 0 1 1 1 0 0 1 1 1 0 0 0 1 OR Truth table ØA. B=(A’+B’)’ A B A’ B’ A’+B’ (A’+B’)’ 0 0 1 1 1 0 0 1 1 0 0 0 1 AND Truth table Wael Qassas/AABU 24

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. A’. B = (A+B’)’ Wael Qassas/AABU 25

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Build the following logical expression using AND, Not Gates only: F=X. Y+Z’ =((X. Y)’. Z’’)’ =((X. Y)’. Z)’ Another example: F= XYZ+Y’Z+XZ’ = ( (XYZ)’. (Y’Z)’. (XZ’)’ )’ Wael Qassas/AABU 26

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. From Demorgans law A+B= (A’. B’)’ (A+B)’= (A’. B’)’’=A’. B’ A. B= (A’+B’)’ (A. B)’= (A’+B’)’’=A’+B’ Wael Qassas/AABU 27

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Simplify the following boolean expression F= (A’BC + A + D )’ = ( A’BCC’ + (A’BC)’C +A+D)’ = ( A’B. 0 + (A’BC)’C +A+D)’ =( 0 + (A’BC)’C +A+D)’ = ( (A+B’+C’)C+A+D)’ = ( AC+B’C+C’C+A+D)’ = ( AC+B’C+ 0 + A +D)’ = (AC+A + B’C + D)’ = ( A + B’C + D)’ = A’ (B’C)’ D’ = A’ D’( B+C’) = A’BD’+A’C’D’ Wael Qassas/AABU 28

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Simplification using boolean algebra: We have the following truth table for logical circuit and we want to implement this in the minimum number of gates: A B C F 0 0 0 1 1 0 0 = A’C(B+B’) +AB’ 0 1 1 1 = A’C+AB’+AC’(B+B’) ; we can reuse AB’C’ 1 0 0 1 =A’C+AB’+AC’ 1 0 1 1 1 1 0 F=A’B’C+A’BC+AB’C’+AB’C+ABC’ = A’B’C+A’BC+AB’(C+C’)+ABC’ Wael Qassas/AABU 29

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Another example: A B C F 0 0 0 1 1 0 0 = A’C + AC(B’+B) +ABC’ 0 1 1 1 = A’C+AC+ AB(C+C’) 1 0 0 0 =A’C+AC+AB 1 0 1 1 1 1 1 F=A’B’C+A’BC+AB’C+ABC’+ABC = A’C(B+B’)+AB’C+ABC’+ABC = C(A+A’)+AB = C+AB Wael Qassas/AABU 30

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Karnaugh Maps Karnaugh map : is a representation for the truth table in a graphical way, which makes the simplification of any boolean function easier. For 3 input boolean function the Karnaugh map will be as follows : 00 01 BC 11 10 A’B’C’ 0 000 A’B’C 001 A’BC 011 A’BC’ 010 AB’C’ 100 AB’C 101 ABC 111 ABC’ 110 A 1 As we can see, each cell represent one raw of the truth table Next step is to fill the map using the truth table output. Wael Qassas/AABU 31

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Simplification using Karnaugh: Let us resolve the previous examples using karnaugh map: A B C F 0 0 0 1 1 0 0 1 1 1 1 0 A 0 1 00 01 0 1 BC 11 10 1 1 0 1 F=A’C+B’C+AC’ Wael Qassas/AABU 32

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Resolve the same example in another way: 0 1 00 01 0 1 BC 11 10 1 1 0 1 F=A’C+AB’+AC’ Wael Qassas/AABU 33

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Karnaugh map for 4 input boolean function CD 00 01 11 10 00 0 1 3 2 0000 0001 0010 01 4 5 7 6 0100 0101 0110 AB 11 12 13 15 14 1100 1101 1110 10 8 9 11 10 1001 1010 Wael Qassas/AABU 34

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Assume we have the boolean function F with 4 inputs: F(A, B, C, D)= ∑ (0, 1 , 4, 6, 8, 11, 13, 15) ØMake the truth table for this function ØWrite the boolean equation for this function (Before simplification) ØSimplify this function using karnaugh map technique ØDraw the simplified equation. 00 01 11 10 00 1 01 1 11 10 1 1 1 Wael Qassas/AABU 35

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Wael Qassas/AABU 36

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Summary MOS transistors are used as switches to implement logic functions. • N-type: connect to GND, turn on (with 1) to pull down to 0 • P-type: connect to +2. 9 V, turn on (with 0) to pull up to 1 Basic gates: NOT, NOR, NAND • Logic functions are usually expressed with AND, OR, and NOT Properties of logic gates • Completeness Ø can implement any truth table with AND, OR, NOT • De. Morgan's Law Ø convert AND to OR by inverting inputs and output Wael Qassas/AABU 37

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Building Functions from Logic Gates We've already seen how to implement truth tables using AND, OR, and NOT -- an example of combinational logic. Combinational Logic Circuit • output depends only on the current inputs • stateless Sequential Logic Circuit • output depends on the sequence of inputs (past and present) • stores information (state) from past inputs We'll first look at some useful combinational circuits, then show to use sequential circuits to store information. Wael Qassas/AABU 38

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Decoder n inputs, 2 n outputs 0 10 100 A B Y 0 1 Y 1 1 Y 2 1 Y 3 1 Wael Qassas/AABU 39

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Decoder n inputs, 2 n outputs • exactly one output is 1 for each possible input pattern 2 -bit decoder Wael Qassas/AABU 40

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. 3 x 8 decoder 0 1 2 3 4 5 6 7 Wael Qassas/AABU 41

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Build the following truth table using Decoder and OR gate A B C F 0 0 0 1 1 0 0 1 1 5 6 1 1 0 1 7 1 1 1 0 3 x 8 decoder 0 1 2 3 4 Wael Qassas/AABU 42

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Multiplexer (MUX) n-bit selector and 2 n inputs, one output 0 1 I 1 1 I 2 0 I 3 S 1 S 0 0 0 1 Wael Qassas/AABU 43

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Multiplexer (MUX) n-bit selector and 2 n inputs, one output • output equals one of the inputs, depending on selector 4 -to-1 MUX Wael Qassas/AABU 44

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Full Adder Add two bits and carry-in, produce one-bit sum and carry-out. S = A + B + Cin Cout = A. B+A. C+B. C A B Cin Cout S 0 0 0 0 1 0 1 0 1 1 1 0 0 0 1 1 0 1 1 1 Wael Qassas/AABU 45

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Full Adder Add two bits and carry-in, produce one-bit sum and carry-out. A B Cin 3 x 8 decoder A B Cin S Cout 0 0 0 0 1 1 0 0 1 0 1 4 1 1 0 0 1 5 6 1 1 1 0 1 2 3 S C 7 Wael Qassas/AABU 46

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Four-bit Adder Wael Qassas/AABU 47

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Combinational vs. Sequential Combinational Circuit • always gives the same output for a given set of inputs Ø ex: adder always generates sum and carry, regardless of previous inputs Sequential Circuit • stores information • output depends on stored information (state) plus input Ø so a given input might produce different outputs, depending on the stored information • example: ticket counter Ø advances when you push the button Ø output depends on previous state • useful for building “memory” elements and “state machines” Wael Qassas/AABU 48

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. R-S Latch: Simple Storage Element R is used to “reset” or “clear” the element – set it to zero. S is used to “set” the element – set it to one. 1 1 0 0 1 1 If both R and S are one, out could be either zero or one. • “quiescent” state -- holds its previous value • note: if a is 1, b is 0, and vice versa Wael Qassas/AABU 49

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Clearing the R-S latch Suppose we start with output = 1, then change R to zero. 1 0 1 1 0 Output changes to zero. 1 1 0 0 Then set R=1 to “store” value in quiescent state. Wael Qassas/AABU 50

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Setting the R-S Latch Suppose we start with output = 0, then change S to zero. 1 1 0 0 1 1 Output changes to one. 0 0 1 1 0 1 Then set S=1 to “store” value in quiescent state. Wael Qassas/AABU 51

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. R-S Latch Summary R=S=1 • hold current value in latch S = 0, R=1 • set value to 1 R = 0, S = 1 • set value to 0 R=S=0 • both outputs equal one • final state determined by electrical properties of gates • Don’t do it! Wael Qassas/AABU 52

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Gated D-Latch Two inputs: D (data) and WE (write enable) • when WE = 1, latch is set to value of D Ø S = NOT(D), R = D • when WE = 0, latch holds previous value ØS = R = 1 Wael Qassas/AABU 53

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Register A register stores a multi-bit value. • We use a collection of D-latches, all controlled by a common WE. • When WE=1, n-bit value D is written to register. Wael Qassas/AABU 54

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Representing Multi-bit Values Number bits from right (0) least significant bit LSb to left (n-1) most significant bit MSb • just a convention -- could be left to right, but must be consistent Use brackets to denote range: D[l: r] denotes bit l to bit r, from left to right 0 15 A = 010100110101 A[14: 9] = 101001 A[2: 0] = 101 May also see A<14: 9>, A 14: 9 especially in hardware block diagrams. Wael Qassas/AABU 55

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Memory Now that we know how to store bits, we can build a memory – a logical k × m array of stored bits. Address Space: number of locations (usually a power of 2) k = 2 n locations Addressability: number of bits per location (e. g. , byte-addressable) • • • m bits Wael Qassas/AABU 56

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. 22 x 3 Memory 1 00 address write enable word select 0 word WE 1 input bits 1 address decoder output bits Wael Qassas/AABU 57

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. 22 x 3 Memory 1 00 address write enable word select 0 word WE 0 input bits 0 1 address decoder output bits Wael Qassas/AABU 58

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. IF we want to build a memory of size 1024 word each word 8 bit a) What is the size of the decoder needed b) How many d- flip flops do we need c) How many And Gates do we need d) How many OR gates do we need e) How many inputs for the OR gates needed Wael Qassas/AABU 59

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. More Memory Details This is not the way actual memory is implemented. • fewer transistors, much more dense, relies on electrical properties But the logical structure is very similar. • address decoder • word select line • word write enable Two basic kinds of RAM (Random Access Memory) Static RAM (SRAM) • fast, maintains data without power Dynamic RAM (DRAM) • slower but denser, bit storage must be periodically refreshed Also, non-volatile memories: ROM, PROM, flash, … Wael Qassas/AABU 60

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. State Machine Another type of sequential circuit • Combines combinational logic with storage • “Remembers” state, and changes output (and state) based on inputs and current state State Machine Inputs Combinational Logic Circuit Outputs Storage Elements Wael Qassas/AABU 61

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Combinational vs. Sequential Two types of “combination” locks 25 4 1 8 4 Combinational Success depends only on the values, not the order in which they are set. 20 30 15 5 10 Sequential Success depends on the sequence of values (e. g, R-13, L-22, R-3). Wael Qassas/AABU 62

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. State The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken. Examples: • The state of a basketball game can be represented by the scoreboard. Ø Number of points, time remaining, possession, etc. • The state of a tic-tac-toe game can be represented by the placement of X’s and O’s on the board. Wael Qassas/AABU 63

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. State of Sequential Lock Our lock example has four different states, labelled A-D: A: B: C: D: The lock is not open, and no relevant operations have been performed. The lock is not open, and the user has completed the R-13 operation. The lock is not open, and the user has completed R-13, followed by L-22. The lock is open. Wael Qassas/AABU 64

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. State Diagram Shows states and actions that cause a transition between states. Wael Qassas/AABU 65

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Finite State Machine A description of a system with the following components: 1. 2. 3. 4. 5. A finite number of states A finite number of external inputs A finite number of external outputs An explicit specification of all state transitions An explicit specification of what causes each external output value. Often described by a state diagram. • • Inputs may cause state transitions. Outputs are associated with each state (or with each transition). Wael Qassas/AABU 66

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. The Clock Frequently, a clock circuit triggers transition from one state to the next. “ 1” “ 0” One Cycle time At the beginning of each clock cycle, state machine makes a transition, based on the current state and the external inputs. • Not always required. In lock example, the input itself triggers a transition. Wael Qassas/AABU 67

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Implementing a Finite State Machine Combinational logic • Determine outputs and next state. Storage elements • Maintain state representation. State Machine Inputs Clock Combinational Logic Circuit Outputs Storage Elements Wael Qassas/AABU 68

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Storage: Master-Slave Flipflop A pair of gated D-latches, to isolate next state from current state. During 1 st phase (clock=1), previously-computed state becomes current state and is sent to the logic circuit. During 2 nd phase (clock=0), next state, computed by logic circuit, is stored in Latch A. Wael Qassas/AABU 69

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Storage Each master-slave flipflop stores one state bit. The number of storage elements (flipflops) needed is determined by the number of states (and the representation of each state). Examples: • Sequential lock Ø Four states – two bits • Basketball scoreboard Ø 7 bits for each score, 5 bits for minutes, 6 bits for seconds, 1 bit for possession arrow, 1 bit for half, … Wael Qassas/AABU 70

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Complete Example A blinking traffic sign • • • No lights on 1 & 2 on 1, 2, 3, & 4 on 1, 2, 3, 4, & 5 on (repeat as long as switch is turned on) 3 4 1 5 2 DANGER MOVE RIGHT Wael Qassas/AABU 71

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Traffic Sign State Diagram Switch on Switch off State bit S 1 State bit S 0 Transition on each clock cycle. Outputs Wael Qassas/AABU 72

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Traffic Sign Truth Tables Outputs (depend only on state: S 1 S 0) Next State: S 1’S 0’ (depend on state and input) Switch Lights 1 and 2 Lights 3 and 4 Light 5 In S 1 S 0 S 1 ’ S 0 ’ 0 X X 0 0 S 1 S 0 Z Y X 1 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 1 Whenever In=0, next state is 00. Wael Qassas/AABU 73

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. Traffic Sign Logic Master-slave flipflop Wael Qassas/AABU 74

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. From Logic to Data Path The data path of a computer is all the logic used to process information. • See the data path of the LC-2 on next slide. Combinational Logic • Decoders -- convert instructions into control signals • Multiplexers -- select inputs and outputs • ALU (Arithmetic and Logic Unit) -- operations on data Sequential Logic • State machine -- coordinate control signals and data movement • Registers and latches -- storage elements Wael Qassas/AABU 75

Copyright © The Mc. Graw-Hill Companies, Inc. Permission required for reproduction or display. LC-2 Data Path Wael Qassas/AABU 76