UNIT V IC MOSFET Amplifiers Outline IC Amplifiers

UNIT -V IC MOSFET Amplifiers

Outline • • • IC Amplifiers IC Biasing –current steering circuit MOSFET current sources Amplifiers with active load CMOS common source and source follower CMOS Differential amplifier

Introduction • Integrated-circuit fabrication technology imposes constraints – large capacitors are not available – very small capacitors are easy to fabricate • One objective is to realize as many functions as possible using MOS transistors only. • Reduction of device size is of great concern.

Why current source needed for IC biasing? • Resistors take too much space on the chip. Source degeneration with resistor is not implemented in ICs. • The goal of a good bias is to ensure drain current (ID) and Drain source voltage. VDS would not change (e. g. , due to temperature variation). One can force ID to be constant using a current source.

IC Biasing Ø Biasing in IC design is based on the use of constant- current sources. Ø A constant dc current (called a reference I) is generated at one location and is then replicated at various other locations for biasing the various stages through a process known as current steering.

Biasing Mechanism for ICs • MOSFET Circuits ØThe basic MOSFET current source ØMOS current-steering circuits Ø The bias currents of the various stages track each other in case of changes in power-supply voltage or in temperature

Current source • Two types of basic gain cells exist: – Common-source (CS) – Common-emitter (CE) • Both are loaded with constant-current source. – This is done because of difficulties associated with fabrication of exact resistances. – It also facilitates increased gain. • These circuits are referred to as current-source loaded / active loaded.

current source - contd… • NMOS current source sinks current to ground • PMOS current sources current from positive supply

Basic current mirror • Simple current-source loads reduce the gain realized in the basic gain cell because of their finite resistance (usually comparable to the value of ro of the amplifying transistor).

n. MOSFET current source Two matching MOSFET transistors connected back-to -back, such that both have the same Gate-to-Source voltage

n. MOSFET current source - contd… • Need: Using the transistors geometries (W/L)1 and (W/L)2 as design parameters create a DC current Io, as long as transistor Q 2 is in Saturation Mode

PMOS Current source

PMOS CURRENT SOURCE - contd…

Basic current mirror - contd… 14

Basic current mirror - contd… • Assume Q 2 to be operating in saturation mode • To ensure that Q 2 is saturated, the circuit to which the drain of Q 2 is to be connected must establish a drain voltage Vo that satisfies the relationship

Basic current mirror - contd… • Identical devices Q 1 and Q 2. The drain current of Q 2, IO, will equal the current in Q 1, IREF, at the value of V 0 that causes the two devices to have the same VDS, that is, at V 0 = VGS. • As V 0 is increased above this value, I 0 will increase according to the incremental output resistance ro 2 of Q 2.

Basic current mirror - contd… VA is proportional to the transistor channel length; thus, to obtain high output-resistance values, current sources are usually designed using transistors with relatively long channels.

Output characteristics

Current mirror circuits - contd… Two performance parameters need to be improved: • The accuracy of the current transfer ratio of the mirror. • The output resistance of the current source.

MOS Cascode current source Ø Q 1 is CS configuration and Q 2 is CG configuration. Ø Current source biasing. 20

MOS Cascode current source - contd…

Small signal of cascode current mirror

Performance of MOS Cascode • Open-circuit voltage gain The cascoding increases the magnitude of the open-circuit voltage gain from Ao to Ao 2 • Output resistance 23

Performance of MOS Cascode • If ro 2 is infinite, then Rin 2 reduces to 1/gm 2. • If ro 2 cannot be neglected, as is always the case in IC amplifiers, the input resistance depends on the value of RL in an interesting fashion. – The load resistance (RL) is divided by the factor (gm 2 ro 2).

Cascode MOS current mirror MOS cascode current mirror requires large load to increase the gain

Cascode MOS current mirror - contd… • Q 1 and Q 3 are always in saturation. • Q 2 and Q 4 both have to be in saturation for current mirror to work. • Condition for saturation – VDS 2 > VGS – Vt – VDS 4 > VGS – Vt

PMOS CASCODE CURRENT MIRROR Working of PMOS cascode is same as NMOS cascode.

Cascoding • To raise the output resistance of the CS or CE transistor, we stack a CG or CB transistor on top. This is cascoding. • The CG or CB transistor in the cascode passes the current gm 1 vi provided by the CS or CE transistor.

Cascoding-contd… • A MOS cascode amplifier operating with an ideal current source load achieves a gain of (gmro)2 = A 02. • To realize the full advantage of cascoding, the load current-source must also be cascoded, in which case a gain as high as 1/2 A 02 can be obtained.

Cascode amplifier with cascode current mirror

Cascode amplifier with cascode current mirror - contd… • Advantage – Much better high-frequency response (high gainbandwidth). – Simpler biasing.

Double Cascoding • If still a higher output resistance and correspondingly higher gain are required, it is still possible to add another level of cascoding • Observe that Q 3 is the second cascode transistor, and it raises the output resistance by (gm 3 ro 3).

Double Cascoding - contd…

The Folded Cascode To avoid the problem of stacking a large number of transistors across a low-voltage power supply, one may use a PMOS transistor.

Folded Cascode-contd… • Double cascoding is possible in the MOS case only. However, the large number of transistors in the stack between the power-supply rails results in the disadvantages of a severely limited output-signal swing. The foldedcascode configuration helps to resolve this issue.

WILSON CURRENT Mirror • A Wilson current mirror is a three-terminal circuit. • It accepts an input current at the input terminal and provides a "mirrored" current source or sink output at the output terminal. • The mirrored current is a precise copy of the input current. • It may be used as a Wilson current source by applying a constant bias current to the input branch. • The circuit is named after George R. Wilson, an integrated circuit design engineer.

MOS Wilson Current Source The drain current of Q 2 to equal the input current and the output configuration assures that the output current equals the drain current of Q 1. 37

MOS Wilson Current Source - contd… • An improved current source which has higher output resistance than the simple current mirror. • The output current is related to the reference current by the equation (assuming the transistors operating in saturation region):

MOS Wilson Current Source - contd… • The reference current I 1 may be approximated by

Small signal-MOS Wilson Current source • The transistor pairs M 1 -M 2 and M 3 -M 4 are exactly matched and the input and output potentials are approximately equal, then in principle there is no static error. • The input and output currents are equal because there is no low frequency or DC current into the gate of a MOSFET.

MOS Wilson Current Source • The threshold voltage of MOS devices is usually between 0. 4 and 1. 0 volts with no body effect depending on the manufacturing technology. • vgs must exceed the threshold voltage by a few tenths of a volt to have satisfactory input-output current match, the total input to ground potential is comparable to 2. 0 volts. • This difference is increased when the transistors share a common body terminal and the body effect in M 4 raises its threshold voltage.

Limitation of Wilson current mirror • The principal limitation on the use of the Wilson current mirror in MOS circuits is the high minimum voltages between the ground connection. • The input and output nodes that are required for properation of all transistors in saturation. • The voltage difference between the input node and ground is vgs 1+vgs 4.

MOS Widlar current source

Summary • Biasing in integrated circuits utilizes current sources. As well, current sources are used as load devices. • The MOS current mirror has a current transfer ratio of (W/L)2/(W/L)1. For a bipolar mirror, the ratio is IS 2/IS 1.

Mos steering circuits 45

MOS steering circuits - contd… • Once a constant current is generated, it can be replicated to provide DC bias currents for the various amplifier stages in the IC. • Current mirrors can obviously be used to implement this current – steering function • The use of a negative DC supply –VSSdoes not change the fact that, by-structure, both transistors, in every mirror pair, have the same VGS voltage.

Mos steering circuits - contd… • Here Q 1 together with R determine the reference current IREF. Transistors Q 1, Q 2, and Q 3 form a two -output current mirror,

Mos steering circuits - contd… • To ensure operation in the saturation region, the voltages at the drains of Q 2 and Q 3 are • constrained as follows: • VD 2, VD 3≥ -VSS +VGS 1 -Vtn • VD 2, VD 3≥ -VSS +Vov 1

Summary • Accurate and stable reference current is generated and then replicated to provide bias current for the various amplifier stages on the chip. • The heart of the current-steering circuitry utilized to perform this function is the current mirror.

CS Amplifier with active load a. Current source acts as an active load. b. Source lead is signal grounded. c. Active load replaces the passive load.

CS Amplifier with active load - contd… ØSmall-signal analysis of the amplifier performed both directly on the circuit diagram and using the smallsignal model explicitly. ØThe intrinsic gain

CS Amplifier with active load - contd…

CG AMPLIFIER AND CD AMPLIFIER

CS Amplifier with source degeneration A CS amplifier with a sourcedegeneration resistance Rs

CS Amplifier with source degeneration • A source-degeneration resistance is called so because of its action is reducing the effective transconductance of the CS stage to gm/(1+gm. Rs). • The output resistance expression of the cascode can be used to find the output resistance of a sourcedegenerated common-source amplifier. • A useful interpretation of the result is that Rs increases the output resistance by the factor (1 + gm. Rs).

CS Amplifier with source degeneration - contd… ØCircuit for small-signal analysis. ØCircuit with the output open to determine Avo. 56

CS Amplifier with source degeneration - contd… • Input resistance • Output resistance • Intrinsic voltage gain The resistance Rs has no effect on Avo • Short-circuit transconductance 57

Summary • A CS amplifier with a resistance Rs in its source lead has an output resistance Ro = (1+gm. RS)ro. The corresponding formula for the BJT case is Ro = [1+gm(Re||rp)]ro.

NMOS amplifier with enhancement load device Driver transistor characteristics and enhancement load curve with transition point

NMOS amplifier with enhancement load device • Dissipation is high since current flows when Vin = 1. • Vout can never reach Vdd (effect of channel). • Vgg can be derived from a switching source (i. e. one phase of a clock, so that dissipation can be significantly reduced. • If Vgg is higher than Vdd, an extra supply rail is required.

Voltage transfer characteristics of NMOS amplifier with enhancement load device

NMOS with Depletion load

NMOS with Depletion load - contd… • Pull-Up is always on – Vgs = 0; depletion • Pull-Down turns on when Vin > Vt • With no current drawn from outputs, Ids for both transistors is equal

NMOS with Depletion load - contd… • Dissipation is high since rail to rail current flows when Vin = Logical 1 • Switching of Output from 1 to 0 begins when Vin exceeds Vt of pull down device • When switching the output from 1 to 0, the pull up device is non-saturated initially and this presents a lower resistance through which to charge capacitors (Vds < Vgs – Vt)

Voltage Transfer Characteristics

NMOS Inverter ID VGS = 3 V X Linear ID vs VDS given by surrounding circuit X VGS = 1 V VDS

CMOS Inverter

CMOS Inverter VOUT vs. VIN VOUT both sat. VDD curve very steep here; only in “C” for small interval of VIN NMOS: cutoff PMOS: triode NMOS: saturation NMOS: triode PMOS: saturation PMOS: cutoff PMOS: triode A B C D E VDD VIN

CMOS Inverter ID ID A B C D E VDD VIN

Important Points • No ID current flow in Regions A and E if nothing attached to output; current flows only during logic transition • If another inverter (or other CMOS logic) attached to output, transistor gate terminals of attached stage do not permit current: current still flows only during logic transition VDD S D VIN S VOUT 1 D D D S S VOUT 2

CMOS Inverter Transfer characteristics • Drain current of NMOS Drain current of PMOS

CMOS Inverter Transfer characteristics At logic threshold, In = Ip

CMOS Inverter Transfer characteristics • If n = p and Vtp = –Vtn •

Common source Amplifier PMOS active load I-V Characteristics CMOS common source Amplifier Driver Transfer Voltage Transfer

Pseudo NMOS Inverter

Pseudo NMOS Inverter

The CMOS common-source amplifier FIG : Common gate CMOS

I-V characteristics

Transfer characteristics

CMOS Common source Amplifier small signal model

CMOS Differential Amplifier • A simple version of a CMOS differential amplifier is shown at the left – The load devices Q 3 and Q 4 are built with PMOS transistors – Q 3 and Q 4 operate as a form of current mirror, in that the small signal current in Q 4 will be identical to the current in Q 3 – Q 3 has an effective impedance looking into its drain of – 1/gm || ro 3 since its current will be a function of the voltage on node vd 1

CMOS Differential Amplifier - contd… • Q 4 has an effective impedance looking into its drain of ro 4 only, since its current will be constant and not a function of vout • The gain of the right hand (inverting) leg will be higher than the gain of the left side • Since all transistors have grounded source operation, there is no body effect to worry about with this CMOS diff amp circuit

CMOS Diff Amp Equivalent Circuit Model

CMOS Diff Amp with Current Mirror Sources

CMOS Diff Amp with Current Mirror Sources

CMOS Diff Amp with Current Mirror Sources

CMOS Diff Amp with Current Mirror Sources - contd… • The advantage of this configuration is that the differential output signal is converted to a single ended output signal with no extra components required. In this circuit, the output voltage or current is taken from the drains of M 2 and M 4.

CMOS Diff Amp with Current Mirror Sources - contd… • The operation of this circuit is as follows. If a differential voltage, VID=VG 1 -VG 2, is applied between the gates, then half is applied to the gatesource of M 1 and half to the gate-source of M 2. The result is to increase ID 1 and decrease ID 2 by equal increment, ∆I.

CMOS Diff Amp with Current Mirror Sources - contd… • The ∆I increase ID 1 is mirrored through M 3 -M 4 as an increase in ID 4 of ∆I. • As a consequence of the ∆I increase in ID 4 and the ∆I decrease in ID 2 , the output must sink a current of 2∆I. • The sum of the changes in ID 1 and ID 2 at the common node VC is zero.

Differential mode

Equivalent Circuit Differential gain is given by

Differential Amplifier • The differential amplifier topology shown at the left contains two inputs, two active devices, and two loads, along with a dc current source • We will define the – differential mode of the input vi, dm = v 1 – v 2 – common mode of the input as vi, cm= ½ (v 1+v 2) • Using these definitions, the inputs v 1 and v 2 can be written as linear combinations of the differential and common modes – v 1 = vi, cm + ½ vi, dm – v 2 = vi, cm – ½ vi, dm

Differential Amplifier - contd… • These definitions can also be applied to the output voltages – Differential mode vo, dm = vo 1 – vo 2 – Common mode vo, cm = ½ (vo 1 + vo 2) • Alternately, these can be written as – vo 1 = vo, cm + ½ vo, dm – vo 2 = vo, cm – ½ vo, dm

Summary-contd. . • Integrated-circuit fabrication technology offers the circuit designer many exciting opportunities, the most important of which is the large number of inexpensive small-area MOS transistors. • An overriding concern for IC designers, however, is the minimization of chip area or “silicon real estate. ” As a result, large-valued resistors and capacitors are virtually absent.

Summary-contd. . • The basic gain cell of IC amplifier is the CS (CE) amplifier with a current-source load. • For an ideal current-source load (i. e. one with infinite output resistance), the transistor operates in an opencircuit fashion and thus provides the maximum gain possible: • Avo = -gmro = -A 0.

Summary-contd. . • The intrinsic gain A 0 is given by A 0 = VA / VT for a BJT and A 0 = VA/(VOV/2) for a MOSFET. For a BJT, A 0 is constant independent of bias current and device dimensions. • For a MOSFET, A 0 is inversely proportional to ID 1/2.