Outline p MOSFET Basics p Ideal MOSFET physics

Outline p MOSFET Basics – – p Ideal MOSFET physics Main parameters : threshold, leakage and speed What MOSFET for what application ? Scaling theory and good design rules of CMOS Devices The Real World – Threshold voltage control limitations – Gate oxide leakage and capacitance scaling p Technological Solution ? – – Gate alternative : High-K and Metal Gate Channel engineering : Strained-Si Alternative devices and substrates Basic logic functions 2

MOSFET Basics 3

Making a Switch with Metal, Oxide and Silicon Vg 0 Vd Metal Oxide n+ Si (p) E Carrier reservoir n+ C = S D Energy Barrier Source Drain x 6

What is an ideal MOS Transistor ? A MOS capacitor is modulating the transport between two carrier reservoir VG=0 V G VS=0 V S VD>0 V D Canal vide : courant nul A VG>0 V G TMOS bloqué OFF-STATE VS=0 V S ++++++ ------- VD>0 V D IDS Canal rempli : courant non nul B TMOS passant ON-STATE MOS capacitance : Field Effect MOSFET 7

n-type & p-type MOSFETs Vg<0 Vg>0 Vd>0 0 n+ Vd<0 0 Metal Oxide Si (p) n+ n. MOSFET Electron conduction p+ Si (n) p+ p. MOSFET Hole conduction 8

MOSFET morphology Gate (Poly-Si) Métal Oxyde Source Drain Semiconducteur Si 9

Basic Physics of MOSFET Log(Idrain) MOSFET switch Ideal switch 3 main parameters ON state Current OFF State Current (Thermal) Threshold (Vth) 1. Threshold Voltage 2. Ion (=speed) 3. Ioff (=stand-by power) Vgate 10

MOSFET Physics n. MOSFET VVGG=V =0 D VS L VD L Tox N ----- +- +- P -+ + gate grille + + channel source --- N + VB « Off State» WS/C BC canal P - d- -- N - - - drain WD/C - -- N -- - VD 11

Threshold Voltage (Vth) L gate channel source WS/C BC drain P - N- -- - - Gate Material Channel Doping WD/C Oxide Thickness N -- - VD 12

On State Current (Ion) Gate Vg-Vth-VDS Lgate Source Drain L 13

Off – State Current (Ioff) Ithermique VG 1<Vth VG 1<VG 2<Vth Idiffusion -- -- -- Ithermique Idiffusion -- -- -VD>0 Modulation of barrier heigth by Capacitive coupling S should be as small as possible VD>0 + dec Ioff Log Idrain 1/S Vth Vgate 14

The Static Leakage Components i) Gate leakage (oxide thickness dependance) Ioff = IS + IG + IB ii) Channel Leakage (Vth and S dependant) iii) Junction leakage (doping dependance) 15

CMOS Scaling CMOS 032 CMOS 045 CMOS 065 CMOS 090 CMOS 120 17

Scaling Theory: Moore’s law Gordon Moore, a co-founder of Intel said in 1965: “Component count per unit area doubles every two years” - Last 40 years : technological advances achieved mainly by reducing transistors size - However current trend of miniaturization causes undesired effects degrading the electrical parameters and transistor performance In reality: • µ decreases • Tox levels-off • Off current increases as transistor size is reduced 18

Ideal MOSFET Basics summary § Threshold Voltage : §Determines the gate voltage transition Vth between Off-state and On-state regimes §Vth depends (at the 1 st order) on the channel doping and gate electrode material § On-State : §MOS gate capacitance lowers channel barrier §electrons(holes) flow from Source to Drain Ion current §Carrier transit time is Cgate*Vgate / Ion the higher Ion the faster the device § Off-State : §MOS gate capacitance potential = 0 §electrons(holes) flow from Source to Drain due to Thermionic current Ioff current §Static Power dissipation is Pstat = VDS * Ioff 19

Part 2. The Real World 20

Vth Control : Short Channel Effects Zone de charge d’espace ZCE L Log Idrain DIBL SCE DIBL BC VDS SCE=Short Channel Effect DIBL=Drain Induced Barrier Lowering Vth 2 Vth 1 Vth Vgate 21

MOSFET Typical Lenghts and Ratios Tox source Lgate, phys gate Tdep drain Xj Lel Good design rules of MOSFET architecture : T ox Xj 1 1 » » ; Lel 30 40 Lel 3 ; Tdep Lel 1 » 3 Vth Vdd 1 » 5 22

Scaling rules (MASTAR Model) VTH(short Mosfet)=VTH(long)-SCE-DIBL æ 2 ö X e Si ç ÷ T ox T dep j SCE = 0. 8 V bi ç 1 + ÷ e ox ç L 2 ÷ L el è el ø æ 2 ö X e Si ç ÷ T ox T dep j DIBL = 0. 8 V ds ç 1 + ÷ e ox ç L 2 ÷ L el è el ø 1 W I dsat = m eff C ox el (Vg -Vth) V dsat 2 Lel T. Skotnicki et al. IEEE EDL, March’ 88 & IEDM’ 1994 23

Why is it so difficult to get a « Good Scaling » ? Oxide Scaling Junction Scaling Lgate, phys source gate Tdep drain Xj Lel Doping increase Subthreshold control 24

Tox/Lel ratio : Gate Oxide Scaling Lgate, phys source Poly-Si gate Tdep drain Xj Lel zz zz 25

N+ Tdep poly = 0. 4 nm P+ 0. 6 nm EOT of polydepletion, A The Gate-Poly Silicon Depletion 20 18 16 14 12 10 8 6 4 2 0 NMOS ( Npoly =1 e 20 cm-3) Vdd scaled with Tox 0 Tp (EOT) @ 1. 8 V 1. 3 V 1. 0 V 0. 7 V 0. 5 V 0. 35 V 0. 25 V 10 20 30 40 CMOS relevant Tox , A Ref. : E. Josse et al. , IEDM’ 99 26

The problem of Gate Leakage Poly-Si Ec Ef Ev Ef Ec 2 Si Ev Substrate Si Si. O 2 P Gate N+ Wpd 2 A reduction in Tox ~ 1 dec increase in gate leakage 29

Impact of Gate Leakage on Circuits 0 0 Igoff 1 1 0 Ig. On 0 Ioffcanal 0 0 In Static Mode, two gate leakages: Ig. Off & Ig. On : increase of Ioff If Tox , Ig , Power 30

Vth/Vdd Ratio If Vdd drops, just decrease the Vth too keep a good Ion. But … Log(I DS ) S degrades at smaller L ! Ioff Vth Vgs 31

What Did We Learn ? Controlling Vth ( Ioff) Increasing Doping Junc. Leak. Ioff (power) increase Scaling Jonctions Rs increase Ion (speed) reduction Scaling Tox Gate leakage Darkspace Higher Ioff Limited Scaling Ion reduction Polydepletion Reducing Vdd (power) Ion reduction 32

Technological Boosters to recover a Healthy Scaling 33

What can we do to retrieve a Healthy Scaling ? Oxide Scaling Junction Scaling Gate Low RSD for lower Xj Better Contact Resistance Less Gate Lekage No Poly Depletion Source Doping increase Drain Ni. Si Subthreshold control Vs Overdrive Ni. Si Silicon channel DIBL-Free Architecture Better Ion at the same overdrive Better Subthreshold Slope 34

Mobility Enhancement 35

Ion Enhancement by materials Transistor Architecture Material Properties Velocity saturation regime Carrier velocity under electric field E in the linear regime: v = µ Ecritical Efield 36

Mobility In Silicon E Shockwave from lattice vibration, or impurities, or gate oxide rugosity every t seconds carrier, mass m* v= 1. 2 Ec m* Small m* : ligth electrons or holes 2. High t (less possible collision) µ=q t m * Effective mass of carrier Linked to valence/conduction bands 37

Gate Capacitance Scaling : High-K dielectrics 50

Figthing against Gate Leakage issue Ec Ef Ev Ef Ec Reducing Tunneling… Increasing Tox ! But without reduction of Cox ! Increasing permitivity HIGH K materials Ev Gate N+ Substrate Si Si. O 2 P Wpd Polydepletion issue Replacing Poly-Si by Metal 51

Figthing against Gate Leakage Context ü Down to 90 nm gate length, N+ and P+ polysilicon gate was used for CMOS integration compatible with oxide or oxynitride gate dielectric. ü Due to aggressive scaling of the gate dielectric, the gate leakage is becoming unacceptably high (>Ioff), requiring the use of high-k dielectric ü Due to the incompatibility of polysilicon gate with high-k dielectric (Fermi pinning, large Vt, mobility degradation) and the need to boost performance (elimination of polydepletion, boron penetration, …), metal gate electrodes will likely be needed ü For bulk technology, two metals with WFs close to the bandgap edges are needed (high channel doping required to control SCE). ü For FDSOI or double gate devices, WFs within 250 me. V from midgap are preferred, requiring more complex integration ü Two integration approaches are considered: gate first and gate last. 52 52

High-k dielectric For EOTs below 20Å, gate leakage current becomes higher than off-state leakage current. High-k dielectric p Pre-deposition clean and post deposition anneals affect the quality of high-k p Large Vt: Fermi pinning at the poly-Si/ Metal oxide interface but occurs also metal gate electrodes p 10 Jg ON (A/Cm²) High-k (Hf. O 2, Zr. O 2, Hf-based or Zr-based, La. O 2, Al 2 O 3, … ALCVD or MOCVD deposition p 100 1 0, 1 2 Dec FD SOI n. MOS, Vg = 1. 1 V Exp data. MASTAR Poly-Si/Si. ON 1 Dec 0, 01 0, 0001 0, 00001 17 MG/Si. ON 2 Dec MG/Hf Si. ON MG/Hf. O 2 19 21 23 CET (A) 25 27 C. Fenouillet et al IEDM 2007 Compatibility of polysilicon gate with high-k is unlikely ! ü High-K At an equivalent CET of Si. ON dielectric, the gate leakage current is reduced by more than 2 decades 53 53

High-k Dielectric : Issues p Mobility degradation - Many publications have reported mobility degradation using high-k dielectrics. - Possible cause is coupling of soft optical phonons in high-k with inversion channel charge carrier p Vt instabilities and reliability and noise issues p Large k and large dielectric thickness result in fringing field (FIBL) and loss of control of the channel by the gate B. Tavel et al, Ph. D Thesis 2002 54 54

Gate Capacitance Scaling : Metal Gates 55

Choosing The « Good Metal » Ec n. MOS Gate poly-Si N+ Metal Gate « N+like » 1. 12 V Mid-gap Gate Ev p. MOS Gate poly-Si P+ Metal Gate « P+like » 56

Metal gate integration p The use of metal gate suppress: – the polysilicon depletion : a reduced CET of 3 -5Å for performance improvement – and suppress the boron penetration problem p Two approaches have been proposed: gate first or gate last – Gate first approach requires to take care of FE contamination tool, metal etching and to the high temperature anneal – Gate last approach (replacement gate): dummy gate removal and replacement, gate dielectric integrity has to be kept But for some applications CMOS requires 2 different metal gates in order to separate WFs for NMOS and PMOS devices (Dual metal gate integration) 57 57

Why is Metal Workfunction so important ? Regular Poly-gate n+/p+ Dual n+/p+ Metal Gate Mid-gap Metal Gate Log Id Vth, p Vth, n Vg Log Id +0. 5 V Vth, p Vth, n Vth, p Vg Id Id Ion, p Vth, n Id Ion, n Vg +25% Polydep reduction Ion, p Vdd Vg Vdd Ion, n Vdd Vg Vdd 58 Vg

Metal gate interest for FDSOI q Why midgap metal gate ? ü Midgap electrode with q Why high-k ? undoped channel : symmetrical Vth for NMOS and PMOS for high Vth applications ü With Band edge gate electrodes (as poly-Si), FDSOI requires very high channel doping > 8 e 18 at/cm 3 for HVT -> Variability degradation 59 59

Device Architecture 60

Device Architecture Xj Tdep GP Bulk PD SOI Scalability ? Scalability as BULK FD SOI Scalability may be better or worse (GP, BOX) FD SON Scalability much improved if GP DG (Delta, Fin. FET, SON, Vertical, Tri. Gate, Omega, etc. , etc. Scalability very much improved REF. : T. Skotnicki, invited paper ESSDERC 2000, pp. 19 -33, edit. Frontier Group 61