CHAPTER 8 Differential and Multistage Amplifiers Microelectronic Circuits

CHAPTER 8 Differential and Multistage Amplifiers Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 1 The basic MOS differential-pair configuration. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 2 The MOS differential pair with a common-mode input voltage VCM. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 3 Circuits for Example 8. 1. Effects of varying VCM on the operation of the differential pair. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

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Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 6 Normalized plots of the currents in a MOSFET differential pair. Note that VOV is the overdrive voltage at which Q 1 and Q 2 operate when conducting drain currents equal to I/2, the equilibrium situation. Note that these graphs are universal and apply to any MOS differential pair Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 7 The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of. VOV. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 10 (a) Differential amplifier for Example 8. 2. (b) Differential half-circuit. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 11 (a) Differential amplifier with current-source loads formed by Q 3 and Q 4. (b) Differential half-circuit of the amplifier in (a). Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 12 (a) Cascode differential amplifier; and (b) its differential half circuit. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 15 The basic BJT differential-pair configuration. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure E 8. 9 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 18 The transfer characteristics of the BJT differential pair (a) can be linearized (b) (i. e. , the linear range of operation can be extended) by including resistances in the emitters. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 21 A differential amplifier with emitter resistances. Only signal quantities are shown (in color). Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 22 Equivalence of the BJT differential amplifier in (a) to the two common-emitter amplifiers in (b). This equivalence applies only for differential input signals. Either of the two common-emitter amplifiers in (b) can be used to find the differential gain, differential input resistance, frequency response, and so on, of the differential amplifier. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 23 The differential amplifier fed in a single-ended fashion. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 24 Equivalent-circuit model of the differential half-circuit formed by Q 1 in Fig. 8. 22(b). Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 26 (a) Definition of the input common-mode resistance Ricm. (b) The equivalent common-mode half-circuit. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 27 Circuit for Example 8. 4. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 28 (a) The MOS differential pair with both inputs grounded. Owing to device and resistor mismatches, a finite dc output voltage. VO results. (b) Application of a voltage equal to the input offset voltage VOS to the input terminals with opposite polarity reduces VO to zero. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 30 A three-stage amplifier consisting of two differential-in, differential-out stages, A 1 and A 2, and a differential-in, single-ended-out stage A 3. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 31 A simple but inefficient approach for differential to single-ended conversion. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 32 (a) The active-loaded MOS differential pair. (b) The circuit at equilibrium assuming perfect matching. (c) The circuit with a differential input signal applied and neglecting the ro of all transistors. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 33 Output equivalent circuit of the amplifier in Fig. 8. 32(a) for differential input signals. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 35 Circuit for determining Ro. The circled numbers indicate the order of the analysis steps. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 36 Analysis of the active-loaded MOS differential amplifier to determine its common-mode gain. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 38 Analysis of the bipolar active-loaded differential amplifier to determine the common-mode gain. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 39 The active-loaded BJT differential pair suffers from a systematic input offset voltage resulting from the error in the currenttransfer ratio of the current mirror. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 40 An active-loaded bipolar differential amplifier employing a folded cascode stage (Q 3 and Q 4) and a Wilson current-mirror load (Q 5, Q 6, and Q 7). Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 41 Two-stage CMOS op-amp configuration. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 42 Bias circuit for the CMOS op amp. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 43 A four-stage bipolar op amp. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 44 Circuit for Example 8. 6. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 45 Equivalent circuit for calculating the gain of the input stage of the amplifier in Fig. 8. 43. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 46 Equivalent circuit for calculating the gain of the second stage of the amplifier in Fig. 8. 43. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 47 Equivalent circuit for evaluating the gain of the third stage in the amplifier circuit of Fig. 8. 43. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 48 Equivalent circuit of the output stage of the amplifier circuit of Fig. 8. 43. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 8. 49 The circuit of the multistage amplifier of Fig. 8. 43 prepared for small-signal analysis. Indicated are the signal currents throughout the amplifier and the input resistances of the four stages. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

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