Lecture 21 OUTLINE The MOSFET contd Pchannel MOSFET

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Lecture 21 OUTLINE The MOSFET (cont’d) • • P-channel MOSFET CMOS inverter analysis Sub-threshold

Lecture 21 OUTLINE The MOSFET (cont’d) • • P-channel MOSFET CMOS inverter analysis Sub-threshold current Small signal model Reading: Pierret 17. 3; Hu 6. 7, 7. 2

P-Channel MOSFET • The PMOSFET turns on when VGS < VT – Holes flow

P-Channel MOSFET • The PMOSFET turns on when VGS < VT – Holes flow from SOURCE to DRAIN is biased at a lower potential than the SOURCE VG VS • VDS < 0 VD GATE P+ ID P+ N VB • IDS < 0 • |IDS| increases with • |VGS - VT| • |VDS| (linear region) • In a CMOS technology, the PMOS & NMOS threshold voltages are usually symmetric about 0, i. e. VTp = -VTn EE 130/230 M Spring 2013 Lecture 21, Slide 2

Long-Channel PMOSFET I-V • Linear region: • Saturation region: m = 1 + (3

Long-Channel PMOSFET I-V • Linear region: • Saturation region: m = 1 + (3 Toxe/WT) is the bulk-charge factor EE 130/230 M Spring 2013 Lecture 21, Slide 3

CMOS Inverter: Intuitive Perspective SWITCH MODELS CIRCUIT VDD G VDD S VDD Rp D

CMOS Inverter: Intuitive Perspective SWITCH MODELS CIRCUIT VDD G VDD S VDD Rp D VOUT = 0 V VOUT = VDD VOUT VIN D G Rn S Low static power consumption, since V one MOSFET is always off in steady state. IN EE 130/230 M Spring 2013 = VDD Lecture 21, Slide 4 VIN = 0 V

Voltage Transfer Characteristic N: sat P: sat VOUT N: off P: lin VDD C

Voltage Transfer Characteristic N: sat P: sat VOUT N: off P: lin VDD C N: sat P: lin A B D E N: lin P: sat N: lin P: off 0 0 EE 130/230 M Spring 2013 VDD Lecture 21, Slide 5 VIN

CMOS Inverter Load-Line Analysis V VIN = VDD + VGSp IDn=-IDp increasin g VIN

CMOS Inverter Load-Line Analysis V VIN = VDD + VGSp IDn=-IDp increasin g VIN = 0 V GS VOUT = VDD + VDSp p =V IN -V DD + VIN = VDD – – VDSp=VOUT-VDD + IDn=-IDp increasing VIN 0 VDD 0 VDSp = VDD EE 130/230 M Spring 2013 VDSp = 0 Lecture 21, Slide 6 VOUT=VDSn

Load-Line Analysis: Region A V GS IDn=-IDp VIN VTn p =V IN -V DD

Load-Line Analysis: Region A V GS IDn=-IDp VIN VTn p =V IN -V DD + – – VDSp=VOUT-VDD + IDn=-IDp 0 VDD 0 EE 130/230 M Spring 2013 Lecture 21, Slide 7 VOUT=VDSn

Load-Line Analysis: Region B V GS IDn=-IDp p =V IN -V DD + VDD

Load-Line Analysis: Region B V GS IDn=-IDp p =V IN -V DD + VDD 0 EE 130/230 M Spring 2013 Lecture 21, Slide 8 – VDSp=VOUT-VDD + IDn=-IDp VDD/2 > VIN > VTn 0 – VOUT=VDSn

Load-Line Analysis: Region D V GS IDn=-IDp p =V IN -V DD + VDD

Load-Line Analysis: Region D V GS IDn=-IDp p =V IN -V DD + VDD 0 EE 130/230 M Spring 2013 Lecture 21, Slide 9 – VDSp=VOUT-VDD + IDn=-IDp VDD – |VTp| > VIN > VDD/2 0 – VOUT=VDSn

Load-Line Analysis: Region E V GS IDn=-IDp VIN > VDD – |VTp| p =V

Load-Line Analysis: Region E V GS IDn=-IDp VIN > VDD – |VTp| p =V IN -V DD + – – VDSp=VOUT-VDD + IDn=-IDp 0 VDD 0 EE 130/230 M Spring 2013 Lecture 21, Slide 10 VOUT=VDSn

MOSFET Effective Drive Current, IEFF M. H. Na et al. , IEDM Technical Digest,

MOSFET Effective Drive Current, IEFF M. H. Na et al. , IEDM Technical Digest, pp. 121 -124, 2002 CMOS inverter chain: V 2 CMOS VDD S inverter: D VIN D GND VOUT S V 3 NMOS DRAIN CURRENT V 1 VDD/2 IH + IL IEFF = 2 V 2 t V 3 p. LH V 1 tp. HL TIME IH VIN = VDD IL 0. 5 VDD NMOS DRAIN VOLTAGE = VOUT EE 130/230 M Spring 2013 IDsat Lecture 21, Slide 11 VIN = ½VDD

Propagation Delay, td CMOS inverter chain: VDD Voltage waveforms: VDD td is reduced by

Propagation Delay, td CMOS inverter chain: VDD Voltage waveforms: VDD td is reduced by increasing IEFF and reducing load capacitance C EE 130/230 M Spring 2013 Lecture 21, Slide 12

Sub-Threshold Current • For |VG| < |VT|, MOSFET current flow is limited by carrier

Sub-Threshold Current • For |VG| < |VT|, MOSFET current flow is limited by carrier diffusion into the channel region. • The electric potential in the channel region varies linearly with VG, according to the capacitive voltage divider formula: • As the potential barrier to diffusion increases linearly with decreasing VG, the diffusion current decreases exponentially: EE 130/230 M Spring 2013 Lecture 21, Slide 13

Sub-Threshold Swing, S log ID NMOSFET Energy Band Profile increasing E n(E) exp(-E/k. T)

Sub-Threshold Swing, S log ID NMOSFET Energy Band Profile increasing E n(E) exp(-E/k. T) Source increasing VGS Drain distance EE 130/230 M Spring 2013 Lecture 21, Slide 14 Inverse slope is subthreshold swing, S [m. V/dec] 0 VT VGS

VT Design Trade-off • Low VT is desirable for high ON current: IDsat (VDD

VT Design Trade-off • Low VT is desirable for high ON current: IDsat (VDD - VT) 1< <2 • But high VT is needed for low OFF current: log ID IOFF, low VT Low VT High VT IOFF, high 0 EE 130/230 M Spring 2013 VT à VT cannot be aggressively reduced! VGS Lecture 21, Slide 15

How to minimize S? EE 130/230 M Spring 2013 Lecture 21, Slide 16

How to minimize S? EE 130/230 M Spring 2013 Lecture 21, Slide 16

MOSFET Small Signal Model • Conductance parameters: A small change in VG or VDS

MOSFET Small Signal Model • Conductance parameters: A small change in VG or VDS will result in a small change in ID low-frequency: high-frequency: EE 130/230 M Spring 2013 Lecture 21, Slide 17

Parasitic Components EE 130/230 M Spring 2013 Lecture 21, Slide 18

Parasitic Components EE 130/230 M Spring 2013 Lecture 21, Slide 18

MOSFET Cutoff Frequency, f. T The cut-off frequency f. T is defined as the

MOSFET Cutoff Frequency, f. T The cut-off frequency f. T is defined as the frequency when the current gain is reduced to 1. input current = output current = v. G here is ac signal CG is approximately equal to the gate capacitance, W L Cox At the cutoff frequency (w. T = 2 pf. T): ® Higher MOSFET operating frequency is achieved by decreasing the channel length L EE 130/230 M Spring 2013 Lecture 21, Slide 19