Chapter 5 MOS Capacitor MOS MetalOxideSemiconductor Vg Vg

Chapter 5 MOS Capacitor MOS: Metal-Oxide-Semiconductor Vg Vg gate metal Si. O 2 Si body MOS capacitor Si. O 2 N+ P-body MOS transistor Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -1

Chapter 5 MOS Capacitor P-Silicon body Si. O 2 N +polysilicon Ec Ec Ef , Ec Ef Ev Ev Gate Si Body Ev This energy-band diagram for Vg = 0 is not the simplest one. Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -2

5. 1 Flat-band Condition and Flat-band Voltage E 0 c =0. 95 e. V Si. O 2 Ec qyg q ys = c. Si + (Ec –Ef ) 3. 1 e. V c. Si 3. 1 e. V =4. 05 e. V Ec, Ef Ec q. Vfb Ev N+ -poly-Si E 0 : Vacuum level E 0 – Ef : Work function E 0 – Ec : Electron affinity Si/Si. O 2 energy barrier 9 e. V P-body 4. 8 e. V Ef Ev The band is flat at the flat band voltage. Ev Si. O 2 Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -3

5. 2 Surface Accumulation Make Vg < Vfb 3. 1 e. V Vox Ec , Ef Ev fs : surface potential, band E 0 q. Vg q fs E c E Ev f M O bending Vox: voltage across the oxide is negligible when the surface is in accumulation. S Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -4

5. 2 Surface Accumulation Vg <Vt Gauss’s Law Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -5

5. 3 Surface Depletion ( Vg > V fb ) q. Vox + + + - - Wdep Si. O V - - - - - depletion layer charge, Q dep P-Si body 2 Ec, Ef q. Vg Ef Ev depletion region Ev M Ec qf s gate O S Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -6

5. 3 Surface Depletion This equation can be solved to yield fs. Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -7

5. 4 Threshold Condition and Threshold Voltage Threshold (of inversion): ns = Na , or fst (Ec–Ef)surface= (Ef – Ev)bulk , or A=B, and C = D Ec q. Vg = q. Vt Ei C = qf. B A D B E E c, f Ev M O S Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -8 Ef Ev

Threshold Voltage Vg = Vfb +φs +Vox At threshold, Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -9

Threshold Voltage + for P-body, – for N-body Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -10

5. 5 Strong Inversion–Beyond Threshold Vg > V t Vg > Vt - - -- gate +++++ q. Vg Si. O 2 V - - - - Q dep Ec - Qinv P - Si substrate Ef Ev E E c, f E v M O S Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -11

Inversion Layer Charge, Qinv (C/cm 2) Vg > Vt Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -12

5. 5. 1 Choice of Vt and Gate Doping Type Vt is generally set at a small positive value so that, at Vg = 0, the transistor does not have an inversion layer and current does not flow between the two N+ regions • P-body is normally paired with N+-gate to achieve a small positive threshold voltage. • N-body is normally paired with P+-gate to achieve a small negative threshold voltage. Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -13

Review : Basic MOS Capacitor Theory fs 2 f. B V accumulation fb depletion Vt Vg inversion Wdep Wdmax = (2 es 2 f. B /q. N a )1/2 µ (fs)1/2 accumulation Vfb depletion Vt inversion Vg Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -14

Review : Basic MOS Capacitor Theory Qdep=- q. Na. Wdep V fb accumulation depletion (a) inversion Vg 0 Vt –q. Na. Wdep total substrate charge, Qs –q. Na. Wdmax Q Qs inv accumulation depletion (b) inversion Vg Vfb Vt accumulation depletion regime inversion regime slope = - Cox Vfb Q acc Qinv slope = - Cox (c) Vfb Vg 0 Vt slope = - C ox Vt accumulation depletion inversion Vg Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -15

5. 6 MOS CV Characteristics MOS Capacitor C-V Meter Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -16

5. 6 MOS CV Characteristics Qs accumulation depletion regime inversion regime Cox C Vfb Vg 0 Vt Qinv slope = - C ox V accumulation fb depletion V Modern Semiconductor Devices for Integrated Circuits (C. Hu) t Vg inversion Slide 5 -17

CV Characteristics Cox accumulation Vfb depletion C Vt Vg inversion In the depletion regime: Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -18

Supply of Inversion Charge May be Limited gate Cox ++ ++ ++ C - - - dep - Wdep Accumulation Depletion P-substrate gate Cox N+ - - - - Inversion DC and AC Wdmax P-substrate DC AC Cox - - - - Cdmax - - - - Inversion Wdmax P-substrate In each case, C = ? Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -19

Capacitor and Transistor CV (or HF and LF CV) Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -20

Quasi-Static CV of MOS Capacitor Cox accumulation Vfb depletion C Vt Vg inversion The quasi-static CV is obtained by the application of a slow linearramp voltage (< 0. 1 V/s) to the gate, while measuring Ig with a very sensitive DC ammeter. C is calculated from Ig = C·d. Vg/dt. This allows sufficient time for Qinv to respond to the slow-changing Vg. Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -21

EXAMPLE : CV of MOS Capacitor and Transistor C MOS transistor CV, QS CV Does the QS CV or the HF capacitor CV apply? HF capacitor CV Vg (1) MOS transistor, 10 k. Hz. (Answer: QS CV). (2) MOS transistor, 100 MHz. (Answer: QS CV). (3) MOS capacitor, 100 MHz. (Answer: HF capacitor CV). (4) MOS capacitor, 10 k. Hz. (Answer: HF capacitor CV). (5) MOS capacitor, slow Vg ramp. (Answer: QS CV). (6) MOS transistor, slow Vg ramp. (Answer: QS CV). Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -22

5. 7 Oxide Charge–A Modification to Vfb and Vt Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -23

5. 7 Oxide Charge–A Modification to Vfb and Vt Types of oxide charge: • Fixed oxide charge, Si+ • Mobile oxide charge, due to Na+contamination • Interface traps, neutral or charged depending on Vg. • Voltage/temperature stress induced charge and traps--a reliability issue Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -24

EXAMPLE: Interpret this measured Vfb dependence on oxide thickness. The gate electrode is N+ poly-silicon. Vfb 10 nm 0 20 nm 30 nm Tox – 0. 15 V – 0. 3 V What does it tell us? Body work function? Doping type? Other? Solution: Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -25

from intercept E 0 , vacuum level yg ys = yg + 0. 15 V Ef , Ec Ec Ef Ev Ev N+ -Si gate Si body N-type substrate, from slope Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -26

5. 8 Poly-Silicon Gate Depletion–Effective Increase in Tox Gauss’s Law Wdpoly = e ox. Eox / q. N poly P+ If Wdpoly= 15 Å, what is the effective increase in Tox? Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -27

Effect of Poly-Gate Depletion on Qinv Wdpoly E c Ef , E v q fpoly • Poly-gate depletion degrades MOSFET current and circuit speed. • How can poly-depletion be minimized? Ec Ef P+ -gate Ev N-substrate Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -28

EXAMPLE : Poly-Silicon Gate Depletion Vox , the voltage across a 2 nm thin oxide, is – 1 V. The P+ polygate doping is Npoly = 8 1019 cm-3 and substrate Nd is 1017 cm-3. Find (a) Wdpoly , (b) fpoly , and (c) Vg. Solution: (a) Wdpoly = e ox. Eox / q. N poly = e ox. Vox / Tox q. N poly - 3. 9 8. 85 10 14 (F/cm) 1 V = -3 19 2 10 7 cm 1. 6 10 19 C 8 10 cm = 1. 3 nm Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -29

EXAMPLE : Poly-Silicon Gate Depletion (b) (c) Is the loss of 0. 11 V from the 1. 01 V significant? Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -30

5. 9 Inversion and Accumulation Charge-Layer Thickness–Quantum Mechanical Effect Average inversion-layer location below the Si/Si. O 2 interface is called the inversion-layer thickness, Tinv Gate -50 -40 -30 -20 -10 Physical T ox 0 10 Si 20 30 40 50 A Effective Tox n(x) is determined by Schrodinger’s eq. , Poisson eq. , and Fermi function. Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -31

Electrical Oxide Thickness, Toxe • Tinv is a function of the average electric field in the inversion layer, which is (Vg + Vt)/6 Tox (Sec. 6. 3. 1). • Tinv of holes is larger than that of electrons because of difference in effective mass. • Toxe is the electrical oxide thickness. at Vg=Vdd Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -32

Effective Oxide Thickness and Effective Oxide Capacitance Toxe = Tox +Wdpoly / 3 +Tinv / 3 C Cox Basic CV with poly-depletion and charge-layer thickness measured data Vg Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -33

Equivalent circuit in the depletion and the inversion regimes (a) General case for both depletion and inversion regions. (b) In the depletion regions (c) Vg Vt Modern Semiconductor Devices for Integrated Circuits (C. Hu) (d) Strong inversion Slide 5 -34

5. 10 CCD Imager and CMOS Imager 5. 10. 1 CCD Imager Deep depletion, Qinv= 0 Exposed to light Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -35

CCD Charge Transfer V 3 V 2 V 1 > V 2 = V 3 (a) - - - depletion region oxide - - - - - P-Si V 2 > V 1 > V 3 V 1 V 2 - - - (b) V 3 V 1 V 3 V 2 V 1 oxide depletion region - - - P-Si V 1 V 2 V 3 V 1 V 2 V 3 V 1 V 2 > V 1 = V 3 (c) - - - depletion region oxide - - - P-Si Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -36

two-dimensional CCD imager Signal out Reading row, shielded from light Charge-to-voltage converter The reading row is shielded from the light by a metal film. The 2 -D charge packets are read row by row. Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -37

5. 10. 2 CMOS Imager PN junction charge collector switch V 1 Amplifier circuit V 2 V 3 Shifter circuit CMOS imagers can be integrated with signal processing and control circuitries to further reduce system costs. However, The size constrain of the sensing circuits forces the CMOS imager to use very simple circuits Signal out Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -38

5. 11 Chapter Summary N-type device: N+-polysilicon gate over P-body P-type device: P+-polysilicon gate over N-body Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -39

5. 11 Chapter Summary or + : N-type device, – : P-type device Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -40

5. 11 Chapter Summary N-type Device (N+-gate over P-substrate) P-type Device (P+-gate over N-substrate) What’s the diagram like at Vg > Vt ? at Vg= 0? Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -41

5. 11 Chapter Summary What is the root cause of the low C in the HF CV branch? Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 5 -42