LowNoise Amplifier 1 RF Receiver Antenna BPF 1

Low-Noise Amplifier 1

RF Receiver Antenna BPF 1 LNA BPF 2 Mixer BPF 3 IF Amp Demodulator RF front end LO 2

Low-Noise Amplifier • First gain stage in receiver – Amplify weak signal • Significant impact on noise performance – Dominate input-referred noise of front end • Impedance matching – Efficient power transfer – Better noise performance – Stable circuit 3

LNA Design Consideration • • Noise performance Power transfer Impedance matching Power consumption Bandwidth Stability Linearity 4

Noise Figure • Definition • As a function of device G: Power gain of the device 5

NF of Cascaded Stages Sin/Nin Sout/Nout G 1, N 1, NF 1 Gi, Ni, NFi GK, NK, NFK • Overall NF dominated by NF 1 [1] F. Friis, “Noise Figure of Radio Receivers, ” Proc. IRE, Vol. 32, pp. 419 -422, July 1944. 6

Simple Model of Noise in MOSFET • Flicker noise Vg Id Vi – Dominant at low frequency • Thermal noise – g: empirical constant 2/3 for long channel much larger for short channel – PMOS has less thermal noise • Input-inferred noise 7

Noise Approximation Noise spectral density 1/f noise Thermal noise dominant Thermal noise Band of interest Frequency 8

Power Transfer and Impedance Matching Rs Vs I • Power delivered to load j. Xs j. XL V RL • Maxim available power • Impedance matching – Load and source impedances conjugate pair – Real part matched to 50 ohm 9

Available Power Equal power on load and source resistors 10

Reflection Coefficient Rs Vs I j. Xs j. XL V RL 11

Reflection Coefficient No reflection Maximum power transfer 12

S-Parameters • Parameters for two-port system analysis • Suitable for distributive elements • Inputs and outputs expressed in powers – Transmission coefficients – Reflection coefficients 13

S-Parameters a 1 b 2 S 21 S 11 S 22 S 12 b 1 a 2 14

S-Parameters • S 11 – input reflection coefficient with the output matched • S 21 – forward transmission gain or loss • S 12 – reverse transmission or isolation • S 22 – output reflection coefficient with the input matched 15

S-Parameters Z 1 Vs 1 I 1 V 1 S I 2 V 2 Z 2 Vs 2 16

Stability Condition • Necessary condition where • Stable iff where 17

A First LNA Example Rs • Assume – – Vs No flicker noise ro = infinity Cgd = 0 Reasonable for appropriate bandwidth • Effective transconductance Rs 4 k. TRs Vs io Vgs gm. Vgs 4 k. Tggm 18

Power Gain • Voltage input • Current output 19

Noise Figure Calculation • Power ratio @ output – Device noise + input-induced noise – Input-induced noise 20

Unity Current Gain Frequency iin Device iout Ai f. T 0 d. B frequency f 21

Small-Signal Model of MOSFET i 2 i 1 V 1 i 1 Rg Cgs V 1 V 2 i 2 Cgd V’gs ri rds Cdb V 2 • • • Cgs Cgd rds Cdb Rg: Gate resistance ri: Channel charging resistance gm. V’gs 22

w. T Calculation i 1 Rg Cgs V 1 i 2 Cgd V’gs ri rds Cdb i 1 Rg Cgs gm. V’gs V 1 Cgd i 2 V’gs ri gm. V’gs 23

w. T of NMOS and PMOS Set: • 0. 25 um CMOS Process* Solve for w. T [2] Tajinder Manku, “Microwave CMOS - Device Physics and Design, ” IEEE J. Solid-State Circuits, vol. 34, pp. 277 - 285, March 1999. 24

Noise Performance • Low frequency – Rsgm >> g ~ 1 – gm >> 1/50 @ Rs = 50 ohm – Power consuming • CMOS technology – gm/ID lower than other tech – w. T lower than other tech 25

Review of First Example • No impedance matching – Capacitive input impedance – Output not matched • Power transfer – S 11=(1 -s. RCgs)/(1+s. RCgs) – S 21=2 Rgm/(1+s. RCgs), R=Rs=RL • Power consumption – High power for NF – High power for S 21 26

Impedance Matching for LNA • • Resistive termination Series-shunt feedback Common-gate connection Inductor degeneration 27

Resistive Termination io Rs Vs RI 4 k. Tggm 4 k. T/Rs 4 k. T/RI Is Rs RI Vgs gm. Vgs • Current-current power gain • Noise figure 28

Comparison with Previous Example • Previous example • Resistive-termination Introduced by input resistance Signal attenuated 29

Summary - Resistive Termination • Noise performance – Low-frequency approximation – Input matched Rs = RI = R • • Broadband input match Attenuate signal Introduce noise due to RI NF > 3 d. B (best case) 30

Series-Shunt Feedback RF Rs Vs RL Ra Rs Cgs Vs • Broadband matching iout RF Vgs gm. Vgs RL • Could be noisy Ra 31

Common-Gate Structure Rs RL Rs 4 k. TRs Vgs gm. Vgs Vs Rs 4 k. TRs Vs 4 k. Tggm RL Vgs RL gm gm. Vgs 4 k. Tggm 32

Input Impedance of CG Structure • Input impedance Yin=gm+s. Cgs • Input-impedance matching – Low frequency approximation – Direct without passive components 1/gm=Rs=50 ohm 33

Noise Performance of CG Structure Signal attenuated 34

Power Transfer of CG Structure • Rs = RL = R = 50 ohm • S 11=0, S 21=1 @ Low frequency 35

Summary – CG Structure • Noise performance – No extra resistive noise source – Independent of power consumption • Impedance matching – Broadband input matching – No passive components • Power consumption – gm=1/50 • Power transfer – Independent of power consumption 36

Inductor Degeneration Structure Rs Vs Rs Lg Zin iin Ls Vs iout Lg Vin Cgs Vgs gm. Vgs Ls Zin 37

Input Matching for ID Structure Rs Zin Vs Ls gm. Ls/Cgs iout Lg Cgs Vgs gm. Vgs • Zin=Rs – IM{Zin}=0 – RE{Zin}=Rs 38

Effective Transconductance Rs Vs Zin Ls gm. Ls/Cgs iout Lg Cgs Vgs gm. Vgs 39

Noise Factor of ID Structure • Calculate NF at w 0 = 0 @ w 0 40

Input Quality Factor of ID Structure I R L C V Rs Vs Ls gm. Ls/Cgs Lg Cgs 41

Noise Factor of ID Structure • Increase power transfer gm. Ls/Cgs = Rs • Decrease NF gm. Ls/Cgs = 0 • Conflict between – Power transfer – Noise performance 42

Further Discussion on NF • Frequency @ w 0 w 2 ~= 1/Cgs/(Lg+Ls) • Input impedance matched to Rs Rs. Cgs=gm. Ls • Suitable for hand calculation and design • Large Lg and small Ls 43

Power Transfer of ID Structure • Rs = RL = R = 50 ohm • @ 44

Computing Av without S-Para Rs Vs Lg Ls 45

Power Consumption 46

Power Consumption • Technology constant – L: minimum feature size – m: mobility, avoid mobility saturation region • Standard specification – Rs: source impedance – w 0: carrier frequency • Circuit parameter – Lg, Ls: gate and source degeneration inductance 47

Summary of ID Structure • Noise performance – No resistive noise source – Large Lg • Impedance matching – Matched at carrier frequency – Applicable to wideband application, S 11<-10 d. B • Power transfer – Narrowband – Increase with gm • Power consumption – Large Lg 48

Cascode LL Vbias Rs Vs M 2 • Isolation to improve S 12 @ high frequency Vo Vd 1 Lg M 1 Ls – Small range at Vd 1 – Reduced feedback effect of Cgd • Improve noise performance 49

LL Rs Rs Vo Lg Vs Ls Vo Cgs M 1 Vs Lg Ls Vgs gm. Vgs LL 50

LNA Design Example (1) M 4 Vbias Rs Vs Lb 1 Cb 1 Input bias Vdd Lvdd Lb 2 Ld Lout M 2 Cb 2 V out Output bias M 3 Tm Cm Lg M 1 Lgnd Ls Off-chip matching [3] D. Shaeffer and T. Lee, “A 1. 5 -V, 1. 5 -GHz CMOS low noise amplifier, ” IEEE J. Solid 51 State Circuits, vol. 32, pp. 745 – 759, May 1997.

LNA Design Example (1) Supply filtering Lvdd M 4 Ld Vbias Rs Vs Lb 1 Cb 1 Lout M 2 M 3 Tm Cm Lg M 1 Lgnd Ls Unwanted parasitics [3] D. Shaeffer and T. Lee, “A 1. 5 -V, 1. 5 -GHz CMOS low noise amplifier, ” IEEE J. Solid 52 State Circuits, vol. 32, pp. 745 – 759, May 1997.

Circuit Details • Two-stage cascoded structure in 0. 6 mm • First stage – W 1 = 403 mm determined from NF – Ls accurate value, bondwire inductance – Ld = 7 n. H, resonating with cap at drain of M 2 • Second – 4. 6 d. B gain – W 3 = 200 mm 53

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LNA Design Example (2) NF = 1 + K/gm gm = gm 1 + gm 2 RB IREF VRF IB 1 M 2 RX Ns Off-chip matching M 1 Cs CB M 4 CX Vout 1 M 5 VB 1 NL Off-chip matching M 7 M 3 M 6 [4] A. Karanicolas, “A 2. 7 -V 900 -MHz CMOS LNA and Mixer, ” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec. 1996. 55

Simplified view 56

LNA Design Example (2) M 8 RB IREF VRF IB 1 M 2 RX Ns M 1 Cs CB M 4 CX Vout 1 M 5 NL VB 1 M 7 M 3 M 6 Bias feedback [4] A. Karanicolas, “A 2. 7 -V 900 -MHz CMOS LNA and Mixer, ” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec. 1996. 57

LNA Design Example (2) M 8 RB IREF VRF IB 1 M 2 RX Ns M 1 Cs CB M 4 CX Vout 1 M 5 NL VB 1 M 7 M 3 M 6 Bias feedback [4] A. Karanicolas, “A 2. 7 -V 900 -MHz CMOS LNA and Mixer, ” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec. 1996. 58

LNA Design Example (2) VA M 8 RB IREF VRF IB 1 M 2 RX Ns M 1 Cs CB DC output = VB 1 M 4 CX Vout 1 M 5 NL VB 1 M 7 M 3 M 6 Bias feedback [4] A. Karanicolas, “A 2. 7 -V 900 -MHz CMOS LNA and Mixer, ” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec. 1996. 59

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LNA Design Example (3) • Objective is to design tunable RF LNA that would: – – Operate over very wide frequency range with very fine selectivity Achieve a good noise performance – Have a good linearity performance – Consume minimum power 61

LNA Architecture • The cascode architecture provides a good input – output isolation • Transistor M 2 isolates the R 1 Miller capacitance • Input Impedance is obtained using the source M 3 degeneration inductor Ls R 2 • Gate inductor Lg sets the resonant frequency • The tuning granularity is LG Input to LNA achieved by the output matching network VDD LD M 2 M 1 Matching Network Output to Mixer LS 62

Matching Network • The output matching tuning network is composed of a varactor and an inductor. • The LC network is used to convert the load impedance into the input impedance of the subsequent stage. • A well designed matching network allows for a maximum power transfer to the load. • By varying the DC voltage applied to the varactor, the output frequency is tuned to a different frequency. 63

Simulation Results - S 11 • The input return loss S 11 is less than – 10 d. B at a frequency range between 1. 4 GHz and 2 GHz Input return loss 64

Simulation results - NF • The noise figure is 1. 8 d. B at 1. 4 GHz and rises to 3. 4 d. B at 2 GHz. Noise Figure 65

Simulation Results - S 22 • By controlling the voltage applied to the varactor the output frequency is tuned by 2. 5 MHz. • The output return loss at 1. 77 GHz is – 44. 73 d. B and the output return loss at 1. 7725 GHz – 45. 69 d. B. S 22 at 1. 77 GHz S 22 at 1. 7725 GHz 66

Simulation Results - S 22 • The output return loss at 2 GHz is – 26. 47 d. B and the output return loss at 1. 9975 GHz – 26. 6 d. B. S 22 at 2 GHz S 22 at 1. 9975 GHz 67

Simulation Results - S 21 • The overall gain of the LNA is 12 d. B S 21 at 1. 4025 GHz 68

Simulation Results - Linearity • The third order input intercept is – 3. 16 d. Bm • -1 d. B compression point ( the output level at which the actual gain departs from theoretical gain) is – 12 d. Bm IIP 3 -1 d. B compression point 69

From an earlier slide: • Flicker noise Vg Id Vi – Dominant at low frequency • Thermal noise – g: empirical constant 2/3 for long channel much larger for short channel – PMOS has less thermal noise • Input-inferred noise Not accurate for low voltage short channel devices 70

Modifications Thermonoise g is called excess noise factor = 2/3 in long channel = 2 to 3 (or higher!) in short channel NMOS (less in PMOS) 71

gdo vs gm in short channel 72

gdo vs gm in short channel 73

Fliker noise • Traps at channel/oxide interface randomly capture/release carriers – Parameterized by Kf and n • Provided by fab (note n ≈ 1) • Currently: Kf of PMOS << Kf of NMOS due to buried channel – To minimize: want large area (high WL) 74

Induced Gate Noise • Fluctuating channel potential couples capacitively into the gate terminal, causing a noise gate current – d is gate noise coefficient • Typically assumed to be 2 g – Correlated to drain noise! 75

real Input impedance Set to be real and equal to source resistance: 76

Output noise current Noise scaling factor: Where for 0. 18 process c=-j 0. 55, g=3, d=6, gdo=2 gm, d = 0. 32 77

Noise factor scaling coefficient: Compare: 78

Noise factor scaling coefficient versus Q 79

Example • Assume Rs = 50 Ohms, Q = 2, fo = 1. 8 GHz, ft = 47. 8 GHz • From 80

Have We Chosen the Correct Bias Point? IIP 3 is also a function of Q 81

If we choose Vgs=1 V • Idens = 175 m. A/mm • From Cgs = 442 f. F, W=274 mm • Ibias = Idens. W = 48 m. A, too large! • Solution 1: lower Idens => lower power, lower f. T, lower IIP 3 • Solution 2: lower W => lower power, lower Cgs, higher Q, higher NF 82

Lower current density to 100 Need to verify that IIP 3 still OK (once we know Q) 83

Lower current density to 100 We now need to re-plot the Noise Factor scaling coefficient - Also plot over a wider range of Q 84

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Recall We previously chose Q = 2, let’s now choose Q = 6 - Cuts power dissipation by a factor of 3! - New value of W is one third the old one 86

• Rs = 50 Ohms, Q = 6, fo = 1. 8 GHz, ft = 42. 8 GHz • Ibias = Idens. W =100 m. A/mm*91 mm=9. 1 m. A • Power = 9. 1 * 1. 8 = 16. 4 m. W • Noise factor scaling coeff = 10 • Noise factor = 1+ wo/wt * 10 = 1+ 1. 8 G/42. 8 G *10 = 1. 42 • Noise figure = 10*log(1. 42) = 1. 52 d. B • Cgs=442/3=147 f. F • Ldeg=Rs/wt=0. 19 n. H • Lg=1/(wo^2 Cgs) –Ldeg = 53 n. H 87

Other architectures of LNAs • Add output load to achieve voltage gain • In practice, use cascode to boost gain • Added benefit of removing Cgd effect 88

Differential LNA Value of Ldeg is now much better controlled Much less sensitivity to noise from other circuits But: Twice the power as the single-ended version Requires differential input at the chip 89

LNA Employing Current Re-Use • PMOS is biased using a current mirror • NMOS current adjusted to match the PMOS current • Note: not clear how the matching network is achieving a 50 Ohm match Perhaps parasitic bondwire inductance is degenerating the PMOS or NMOS transistors? 90

Combining inductive degeneration and current reuse Current reuse to save power Larger area due to two degeneration inductor if implemented on chip NF: 2 d. B, Power gain: 17. 5 d. B, IIP 3: 6 d. Bm, Id: 8 m. A from 2. 7 V power supply Can have differential version F. Gatta, E. Sacchi, et al, “A 2 -d. B Noise Figure 900 MHz Differential CMOS LNA, ” IEEE JSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444 -1452 91

At DC, M 1 and M 2 are in cascode At AC, M 1 and M 2 are in cascade S of M 2 is AC shorted Gm of M 1 and M 2 are multiplied. Same biasing current in M 1 & M 2 LIANG-HUI LI AND HUEY-RU CHUANG, MICROWAVE JOURNAL® from the February 2004 issue. 92

• IM 3 components in the drain current of the main transistor has the required information of its nonlinearity • Auxiliary circuit is used to tune the magnitude and phase of IM 3 components • Addition of main and auxiliary transistor currents results in negligible IM 3 components at output Sivakumar Ganesan, Edgar Sánchez-sinencio, And Jose Silva-martinez IEEE Transactions On Microwave Theory And Techniques, Vol. 54, No. 12, December 2006 93

MOS in weak inversion has speed problem MOS transistor in weak inversion acts like bipolar Bipolar available in TSMC 0. 18 technology (not a parasitic BJT) Why not using that bipolar transistor to improve linearity ? 94

Inter-stage Inductor gain boost Inter-stage inductor with parasitic capacitance form impedance match network between input stage and cascoded stage boost gain lower noise figure. Input match condition will be affected 95

Folded cascode Low supply voltage Ld reduces or eliminates Effect of Cgd 1 Good f. T 96

Design Procedure for Inductive Source Degenerated LNA Noise factor equations: 97

Targeted Specifications • • • Frequency Noise Figure IIP 3 Voltage gain Power 2. 4 GHz ISM Band 1. 6 d. B -8 d. Bm 20 d. B < 10 m. A from 1. 8 V 98

Step 1: Know your process • A 0. 18 um CMOS Process • Process related – – tox = 4. 1 e-9 mm e = 3. 9*(8. 85 e-12) F/m m = 3. 274 e-2 m^2/V. s Vth = 0. 52 V • Noise related – – a = gm/gdo d/g ~ 2 g ~ 3 c = -j 0. 55 99

Step 2: Obtain design guide plots 100

Insights: • gdo increases all the way with current density Iden • gm saturates when Iden larger than 120 m. A/mm – Velocity saturation, mobility degradation ---- short channel effects – Low gm/current efficiency – High linearity • a deviates from long channel value (1) with large Iden 101

Obtain design guide plots 102

Insights: • f. T increases with Vod when Vod is small and saturates after Vod > 0. 3 V --- short channel effects • Cgs/W increases slowly after Vod > 0. 2 V • f. T begins to degrade when Vod > 0. 8 V – gm saturates – Cgs increases • Should keep Vod ~0. 2 to 0. 4 V 103

Obtain design guide plots knf vs input Q and current density 3 -D plot for visual inspection 2 -D plots for design reference 104

Design trade-offs • For fixed Iden, increasing Q will reduce the size of transistor thus reduce total power --- noise figure will become larger • For fixed Q, reducing Iden will reduce power, but will increase noise factor • For large Iden, there is an optimal Q for minimum noise factor, but power may be too high 105

Obtain design guide plots Linearity plots : IIP 3 vs. gate overdrive and transistor size 106

Insights: • MOS transistor IIP 3 only, when embedded into actual circuit: – Input Q will degrade IIP 3 – Non-linear memory effect will degrade IIP 3 – Output non-linearity will degrade IIP 3 • IIP 3 is a very weak function of device size • Generally, large overdrive means large IIP 3 – But the relationship between IIP 3 and gate overdrive is not monotonic – There is a local maxima around 0. 1 V overdrive 107

Step 4: Estimate f. T Small current budget ( < 10 m. A ) does not allow large gate over drive : Vod ~ 0. 2 V ~ 0. 4 V f. T ~ 40 ~ 44 GHz 108

Step 4: Determine Iden, Q and Calculate Device Size Gm/W~0. 4 Select Iden = 70 m. A/mm, =>Vod~0. 23 V 109

If Q = 4, IIP 3 will have enough margin: Estimated IIP 3: IIP 3(from curve) – 20 log(Q) = 8 -12 = -4 d. Bm Specs require: -8 d. Bm 110

Q=4 and Iden = 70 m. A/mm meet the noise factor requirement 111

Gm=0. 4*128 ~ 50 m. S f. T = gm/(Cgs*2 pi) = 48 GHz 112

Step 6: Simulation Verification Large deviation 113

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Comparison between targeted specs and simulation results Parameter Noise Figure Drain Current Voltage gain IIP 3 P 1 d. B S 11 Power supply Target 1. 6 d. B < 10 m. A 20 d. B -8 d. Bm 1. 8 V Simulated 0. 8 d. B 8 m. A 21 d. B -6. 4 d. Bm -20 dbm -17 d. B 1. 8 V 115