Lab 3 Introduction to programmable devices FPGA CPLD

Lab 3: Introduction to programmable devices (FPGA, CPLD), Hardware Description Language (VHDL), and the use programming tool. N S Ghedia Amit Degada Gaurav Bhatti

Presentation Outline • • • Why HDLs Feature of HDL Implementation Design Cycle Advantage of HDL A Bief History of VHDL Writing Code

VHDL A First Look

Goal of the Lab • Introduction to CPLD and FPGA will be covered in theory class. • This lab give you basic idea how to construct the code in VHDL-----VHDL A First Look • Elements of VHDL

Sequential Language • Statements execute one at a time in a sequential manner • Sequence of the statements is important as in case of conventional language

Why HDLs? • In software everything is sequential • Sequence of statements is significant, since they are executed in that order • In hardware events are concurrent, so a software language cannot be used for describing and simulating hardware.

Example • C = (not (X) and Y) or (not (X)) Case 1 A = not X B = A and Y C = A or B Result: C=1 Case 2 B = A and Y C = A or B A = not X Result: C=0 Case 3 C = A or B A = not X B = A and Y Result: C=0

Features of HDLs • • • Concurrent Descriptions Synchronizing mechanisms between concurrent flows Event Scheduling Special object types and data types Hierarchy

HDL Implementation Design Cycle

Advantage of Using Hardware Description Language • Designs can be described at various levels of abstractions • Top-Down Approach and hierarchical designs for large projects • Functional Simulation Early in the Design Flow • Automatic Conversion of HDL Code to Gates With user level control. Consistent quality. Fast. • Early Testing of Various Design Implementations Due to fast synthesis, there is a scope for trying different implementations. • Design Reuse Technology independence, standardization, portability, ease of maintenance. All this results in low risk, high convergence, fast time to market, more money.

A Brief history of HDLs • VHDL stands for Very high speed integrated circuit Hardware Description Language • Funded by the US Department of Defense in the 70's and 80's • Originally meant for design standardisation, documentation, simulation and ease of maintenance. • Established as IEEE standard IEEE 1076 in 1987. An updated standard, IEEE 1164 was adopted in 1993. In 1996 IEEE 1076. 3 became a VHDL synthesis standard. • Today VHDL is widely used across the industry for design description, simulation and synthesis.

What is VHDL? VHDL Stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.

Feature of VHDL • VHDL is the combination of following languages - Sequential Language - Concurrent Language - Net-List Language - Simulation Language - Timing Specifications - Test Language • Powerful Language Constructs - e. g. if –then –else / when –else etc. • Design Hierarchies to create modular design • Support for Design Libraries • Portable and Technology independent

About VHDL • VHDL is not case sensitive • VHDL is a free form language. You can write the whole program on a single line. -- This is a VHDL comment entity my_exor is -- one more comment Port(. . . ); end my_exor;

my EXOR gate -- This is my first VHDL program library IEEE; use IEEE. std_logic_1164. all; entity my_exor is port (ip 1 : in std_logic; ip 2 : in std_logic; op 1 : out std_logic ); end my_exor; entity declaration - describes the boundaries of the object. It defines the names of the ports, their mode and their type.

my EXOR gate library IEEE; use IEEE. std_logic_1164. all; entity my_exor is port (ip 1 : in std_logic; ip 2 : in std_logic; op 1 : out std_logic ); end my_exor; entity - defines the interface. Mode of the port : Direction of flow. It can be in, out, inout, buffer

my EXOR gate library IEEE; use IEEE. std_logic_1164. all; entity my_exor is port (ip 1 : in std_logic; ip 2 : in std_logic; op 1 : out std_logic ); Mode of the port : end my_exor; It can be in, out, inout, buffer entity - defines the interface. std_logic is the type of the port. Standard logic is defined by the standard IEEE 1164. It is defined in the IEEE library. Any node of type std_logic can take 9 different values. ‘ 0’ , ’ 1’ , ’H’ , ’L’ , ’Z’ , ’U’ , ’X’ , ’W’ , ’-’

my EXOR gate library IEEE; use IEEE. std_logic_1164. all; entity my_exor is port (ip 1 : in std_logic; ip 2 : in std_logic; op 1 : out std_logic ); end my_exor; Library : Collection of design elements, type declarations, sub programs, etc.

my EXOR gate library IEEE; use IEEE. std_logic_1164. all; entity my_exor is port (ip 1 : in std_logic; ip 2 : in std_logic; op 1 : out std_logic ); Mode of the port : end my_exor; It can be in, out or inout Library : Collection of design elements, type declarations, sub programs, etc. entity - defines the interface. std_logic is the type of the port It is defined in the IEEE library. Any node of type std_logic can take 9 different values. ‘ 0’ , ’ 1’ , ’H’ , ’L’ , ’Z’ , ’U’ , ’X’ , ’W’ , ’-’ architecture my_exor_beh of my_exor is begin op 1 <= (ip 1 and (not ip 2)) or The architecture describes the (ip 2 and (not ip 1)); behaviour (function), end my_exor_beh; interconnections and the relationship between different inputs and outputs of the entity.

my EXOR gate library IEEE; use IEEE. std_logic_1164. all; entity my_exor is port (ip 1 : in std_logic; ip 2 : in std_logic; op 1 : out std_logic ); Mode of the port : end my_exor; It can be in, out or inout architecture my_exor_beh of my_exor is begin op 1 <= (ip 1 and (not ip 2)) or (ip 2 and (not ip 1)); end my_exor_beh; configuration my_exor_C of my_exor is for my_exor_beh end for; end my_exor_C; Library : Collection of design elements, type declarations, sub programs, etc. entity - defines the interface. std_logic is the type of the port It is defined in the IEEE library. Any node of type std_logic can take 9 different value. ‘ 0’ , ’ 1’ , ’H’ , ’L’ , ’Z’ , ’U’ , ’X’ , ’W’ , ’-’ The architecture describes the behaviour(function), interconnections and the relationship between different inputsand outputs. The configuration is optional. It defines the entity architecture bindings. More about configurations later.

Internal connections are made using signals. Signals are defined inside the architecture my_exor_beh of my_exor is signal temp 1 : std_logic; signal temp 2 : std_logic; begin. . . end my_exor_beh;

my EXOR with internal signals library IEEE; use IEEE. std_logic_1164. all; entity my_exor is port (ip 1 : in std_logic; ip 2 : in std_logic; op 1 : out std_logic ); end my_exor; architecture exor_w_sig of my_exor is signal temp 1, temp 2 : std_logic; begin temp 1 <= ip 1 and (not ip 2); temp 2 <= ip 2 and (not ip 1); op 1 <= temp 1 or temp 2; end exor_w_sig; configuration my_exor_C of my_exor is for exor_w_sig end for; end my_exor_C;

Quaratus II Simulating VHDL Code

Starting New Project • Open Quartus II (7. 2) • Start Wizard File->New Project Wizard • Click Next , Specify Name of Project and the directory and click Next • Specify files you want to add and click Next • Specify FPGA and click Next , Next and Finish – Cyclone II , EP 2 C 20 F 484 C 6

Turn off Incremental Compilation • Assignments->Settings->Compilation Process Settings -> Incremental Compilation

Operating VHDL Files • Create new files File->New • Add existing files and set compilation order Assignments ->Settings->Files • Changing Top level entity Assignments->General ->Top-level entity • Analyze the project : Push Button • View resource utilization at “Compilation Report”

Viewing Synthesis results • RTL Synthesis – Tools -> Netlist Viewers -> RTL viewer • Technology Synthesis – Tools -> Netlist Viewers -> Technology map viewer

Setting Simulation Add Vector file File->New Add signals Edit->Insert node or bus Press the “Node Finder” and select signals Change Simulation Time Edit->End Time, Edit->Grid Size

Setting waveforms Use the buttons on the left side to generate input signals

Running simulation • Save the Waveform file and go to : Assignments-> Settings->Simulator settings • Set simulation mode to Functional and choose your file as simulation input • Ctrl+Shift+K – Starts the simulation • Look on The simulation report

VHDL Elements

Elements of VHDL Basic building blocks Entity Architecture Language elements Concurrent Statements Component Instantiation Sequential Statements Configuration & Generics Package Attributes Will be Covered later

Programming method A structural design methodology is used to - split design into manageable units - silicon vendor provides the libraries which can be used to instantiate components that represent device specific resources and optimized structures - synthesis tools have in-built algorithms that find the optimal solutions regardless of form of description.

VHDL identifiers Identifiers are used to name items in a VHDL model. A basic identifier may contain only ‘A’ to ‘Z’ ‘a’ to ‘z’ ‘ 0’ to ‘ 9’ underline character ‘_’ • must start with a alphabet • may not end with a underline character • must not include two successive underline characters VHDL is not case sensitive

VHDL identifiers VHDL supports a variety of data types and operators. VHDL is a strongly typed language. Users can define their own data types and operators in user defined packages. There are three basic object types in VHDL. signal - represents interconnections that connect components and ports. variable - used for local storage within a process. constant - a fixed value The object type could be a scalar or an array (unidimensional as well as multidimensional)

VHDL Data Types Data types are very important for any programming language VHDL Contains a series of pre-defined data types, specified through IEEE 1076 and IEEE 1164 standards. Data types defination can be found in the Packages and Library. VHDL Supports Following Datatypes Bit Boolean Integer Natural Real

Bit literal Used to represent value of a digital system Values allowed are ‘ 0’ and ‘ 1’ Bit vector literal is expressed as a string of bit literals enclosed in double quotes eg ‘ 1’ , ‘ 0’, “ 1011” , X” 7 CEF” ( hex ), O” 5673” ( octal ) eg signal valid : bit

Boolean literal represents true or false values allowed are true(TRUE, True) false(FALSE, False) eg: signal busactive : boolean; . . . busactive <= true; . . . if (busactive and valid = ‘ 1’) then data_out <= din; valid_out <= ‘ 1’; end if;

Basic Building Blocks Entity A design’s interface signals to the external circuitry. Architecture Describes a design’s behavior and functionality. Configuration Binds an entity to an architecture when there are multiple architectures for a single entity. Package Contains frequently used declarations, constants, functions, procedures, user data types and components. Library Consists of all the compiled design units like entities, architectures, packages and configurations

A Typical Example library IEEE; use IEEE. std_logic_1164. all; entity my_exor is port (ip 1 : in std_logic; ip 2 : in std_logic; op 1 : out std_logic ); Mode of the port : end my_exor; It can be in, out or inout architecture my_exor_beh of my_exor is begin op 1 <= (ip 1 and (not ip 2)) or (ip 2 and (not ip 1)); end my_exor_beh; configuration my_exor_C of my_exor is for my_exor_beh end for; end my_exor_C; Library : Collection of design elements, type declarations, sub programs, etc. entity - defines the interface. std_logic is the type of the port It is defined in the IEEE library. Any node of type std_logic can take 9 different value. ‘ 0’ , ’ 1’ , ’H’ , ’L’ , ’Z’ , ’U’ , ’X’ , ’W’ , ’-’ The architecture describes the behaviour(function), interconnections and the relationship between different inputsand outputs. The configuration is optional. It defines the entity architecture bindings. More about configurations later.

Library Syntax Before accessing any unit in a library it needs to be declared. STD and WORK need not be declared. Its syntax is library_name ; components declared inside a library can be accessed by the ‘USE’ statement use library_name. package_name. item_name ; use library_name. item_name ; Note ‘library’ and the ‘use’ statement is part of the entity which follows immediately. So library should be defined before EACH entity declaration even if it is in the same vhdl file. The libraries are mapped into a directory which is tool dependant and these settings are generally configurable.

Library Example library IEEE ; use IEEE. std_logic_1164. all use IEEE. std_logic_unsigned. all library my_library ; use my_library. my_package. all

Std_logic type • • • std_logic type is a data_type defined in the std_logic_1164 package of IEEE library It defines a number of states for a digital signal which helps in simulation and debugging It is an enumerated type and is defined as type std_logic is (‘U’, ‘X’, ‘ 0’, ‘ 1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’); where ‘U’ - Uninitialised ‘X’ - Forcing Unknown ‘ 0’ - Forcing 0 ‘ 1’ - Forcing 1 ‘Z’ - High Impedance ‘W’ - Weak Unknown ‘L’ - Weak 0 ‘H’ - Weak 1 ‘-’ - Dont Care

Resolution Function When more than one driver is driving a signal then the simulator calls the resolution function for that type to assign a value. eg. When two std_logic drivers are driving ‘ 1’ and ‘ 0’ simultaneously the signal is assigned the value ‘X’. A table resolves every possible combination and returns the appropriate value to be assigned. If there is no resolution function, multiple drivers are not allowed.

Entity • Equivalent to pin configuration of an IC Syntax entity_name is port (port_list); end entity_name Example: entity not_gate is port ( a 1, a 2, a 3: in std_logic; a 4, a 5, a 6: in std_logic; b 1, b 2, b 3: out std_logic; b 4, b 5, b 6: out std_logic ); end not_gate; 1 14 2 13 3 12 4 11 5 10 6 9 7 8

Entity VHDL design description must include, - only one entity - at-least one corresponding architecture. Entity declaration - Defines the input and output ports of the design - Each port in the port list must be given - a name - data flow direction - a type Can be used as a component in other entities after being compiled into library

Entity • Proper documentation of the ports in an entity is very important • A specified port should have a self explanatory name that provides information about its function. • Port should be well documented with the comments at the end of the line providing additional information about the signal • Consider the example of ALU in 1 cin in 2 opsel mode cout ALU result

Entity entity ALU is port ( in 1 : in std_logic_vector(3 downto 0); -- first operand in 2 : in std_logic_vector(3 downto 0); -- second operand opsel: in std_logic_vector(3 downto 0); -- operation sel. cin : in std_logic; -- carry input mode: in std_logic; --mode arithmetic/logic result: out std_logic_vector (3 downto 0); --operation result cout: out std_logic); -- carry output end ALU

Modes • Signal in the port has a mode which indicates the driver direction • Mode also indicate whether or not the port can be read from within the entity • Four types of modes are used in VHDL - mode IN - mode OUT - mode INOUT - mode BUFFER The assignment of hardware I/O buffers to the ports (push-pull, tri-state, differential output, etc. ) depends on the implementation and the target technology. Use of buffer ports is not recommended.

Mode IN • Value can be read but not assigned Example: entity driver is port ( A: in std_logic; B: out std_logic; data: inout std_logic; count: buffer std_logic ); end driver; Entity Port signal A Driver reside outside the entity

Mode OUT • Value can be assigned but not read Entity Example: entity driver is port ( A: in std_logic; B: out std_logic; data: inout std_logic; count: buffer std_logic ); end driver; Port signal B Driver reside inside the entity

Mode INOUT • Value can be read and assigned Example: entity driver is port ( A: in std_logic; B: out std_logic; data: inout std_logic; count: buffer std_logic ); end driver; Port signal Entity data Driver may reside both inside and outside the entity

Mode BUFFER • Output port with internal read capability Entity Example: entity driver is port ( A: in std_logic; B: out std_logic; data: inout std_logic; count: buffer std_logic ); end driver; Port signal count Driver reside inside the entity

Architecture Can contain only concurrent statements Design can be described in an architecture using various levels of abstraction - to facilitate faster design - better understanding - lesser complexity AN ENTITY CAN HAVE MORE THAN ONE ARCHITECTURE …. WHY? ? There can be no architecture without an entity

Architecture An architecture specifies the behavior, function, interconnections and the relationship between the inputs and the outputs of an entity. • An entity can have more than one architecture. There can be no architecture without an entity. Each architecture is bound to an entity using the configuration statement. Architectures can have various abstraction levels and implementations to facilitate faster design, better understanding, better performance and lesser complexity. Some of these aspects may be mutually exclusive where some amount of compromise needs to be arrived at.

Architecture Syntax architecture_name of entity_name is [declarations] begin [statements] end [ architecture_name ]; Architecture can contain only concurrent statements

Architecture bodies Three types 1. Behavioral 2. Data flow 3. Structural

Architecture bodies Behavioral -Also known as High level descriptions - Consist of set of assignment statements to represent the behavior - no need to focus on the gate level implementation of design Architecture gates of and_gate is begin process (a, b) if a = ‘ 1’ and b= ‘ 1’ then c<= ‘ 1’; else c<= ‘ 0’; end if; end process; end gates;

Architecture bodies Dataflow Architecture gates of and_gate is begin - use concurrent signal assignment statements c<= a AND b; end gates;

Architecture bodies Structural • Component from the libraries are connected together • Designs are hierarchical • Each component can be individually simulated • Consist of VHDL net-list It is possible to mix three modeling style in single architecture body

Configuration A configuration statement selects one of several architectures for a single entity. Components within architectures can also be chosen. Configuration can be used for version control Configuration is ignored by the synthesizer. Unless specified, the last compiled architecture is used for simulation Configuration saves compile time when some components need substitution in a large design.

Configuration Syntax configuration_name of entity_name is for architecture_name for instance_name: component_name use entity library_name. entity_name(architecture_name); end for; end configuration_name;

Configuration Example configuration my_design_struct_C of my_design is for my_design_struct for u 0: and 2 use entity work. and 2(and 2_struct); end for; for u 1: or 2 use configuration work. or 2_struct_C; end for; for all: nand 2 use entity mylib. nand 2(nand 2_beh); end for; end my_design_struct_C;

Now Something on Operators

Operators • Logical Lowest priority • Relational • Shift • Adding • Multiplying • Miscellaneous Highest priority

Logical operators And or nand nor xnor are define for - types BIT and BOOLEAN - One dimensional array of BIT and BOOLEAN not

Logical operators Example Port ( a, b, c : bit vector (3 downto 0); d, e, f, g : bit_vector (1 downto 0); h, I, j, k : bit; l, m, n, o, p : boolean ); a <= b and c; d <= e or f or g ; h <= (i nand j) nand k ; l <= (m xor n) and ( o xor p);

Logical operators Example Port ( a, b, c : bit vector (3 downto 0); d, e, f, g : bit_vector (1 downto 0); h, I, j, k : bit; l, m, n, o, p : boolean ); a <= b and e; h <= i and j or k ; h <= i or l ; l <= m nand n nand o nand p; Operand must be same size Parenthesis required Operand must be same type Parenthesis required

Signal assignments <= is signal assignment operator An assignment to a signal defines a driver on that signal Z <= A ; A Z

Relational (conditional) operator Are used to check the conditions = /= < <= > >= “=“ and “/=“ are predefine for all types (except file) “<“, “<=“, ”>”, and “>=“ are predefine for - integer types - Enumerated types - one dimensional arrays of enumeration and integer types

Relational operator No numerical meaning is associated with vector Elements of a vector are just a collection of objects of the same type 1 1 1 Not 7 … but a set of three ones

Relational operator For the array type operands are aligned to left and compared to right Arrays of different length Align left Compare to right 1 1 0 1 1 greatest

Shift Operators sll srl sla -sll shift left logical -srl shift right logical - sla shift left arithmetic - sra shift right arithmetic - rol rotate left logical - ror rotate right logical sra rol ror

Shift Operators Each operator - takes an array of BIT or BOOLEAN as left operand - Integer value as right operand example: A is bit_vector equal to “ 10010101” A sll 2 is “ 01010100” ( shift left logical, filled with ‘ 0’) A srl 3 is “ 00010010” ( shift right logical, filled with ‘ 0’) A sla 3 is “ 10101111” ( shift left arithmetic, filled with right bit) A sra 2 is “ 11100101” ( shift right arithmetic, filled with left bit) A rol 3 is “ 10101100” (rotate left)

Arithmatic operators + - & Concatenation operator (&) - operands can be one dimensional array or element type - “& works on vector only Example: signal a: std_logic_vector (5 downto 0); signal b, c, d: std_logic_vector (2 downto 0); begin b<= ‘ 0’ & c(1) & d(2) a<= c & d; end;

Operators and Operators Prescedence xnor and shift VHDL’ 93 only !! Precedence can be overridden by use of parentheses. Precedence of operators is maintained even after overloading.

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