FPGA Editor Viewing and Editing a Routed Design

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FPGA Editor: Viewing and Editing a Routed Design © 2003 Xilinx, Inc. All Rights

FPGA Editor: Viewing and Editing a Routed Design © 2003 Xilinx, Inc. All Rights Reserved

Objectives After completing this module, you will be able to: • • Use the

Objectives After completing this module, you will be able to: • • Use the FPGA Editor to view device resources Connect the internal nets of an FPGA to output pins (Insert Probes) Determine the specific resources used by your design Make minor changes to your design without reimplementing FPGA Editor - 18 - 3 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Changed the order of the sections - moved “Viewing

Rhett Whatcott: v 6. 1: Changed the order of the sections - moved “Viewing Device Resources…” as 2 nd section. Outline • • • FPGA Editor - 18 - 4 FPGA Editor Basics Viewing Device Resources and Constrained Paths Adding a Probe Making Minor Changes Summary Appendix: Creating a Macro © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Next slide was removed, titled: FPGA Editor Input Files

Rhett Whatcott: v 6. 1: Next slide was removed, titled: FPGA Editor Input Files • The FPGA Editor is a graphical application – – • What Does the FPGA Editor Do? Displays device resources Precise layout of chosen device The FPGA Editor is commonly used to: – – View device resources Make minor modifications • • – FPGA Editor - 18 - 5 Done late in the design cycle Does not require reimplementation of the design Insert Probes • Used for in circuit © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

When to Use the FPGA Editor • Use the FPGA Editor to: – –

When to Use the FPGA Editor • Use the FPGA Editor to: – – – • View the design’s layout Drive a signal to an output pin for testing (inserting a probe) Add logic or special architectural features to your design without having to recompile the design Do not use the FPGA Editor to: – – FPGA Editor - 18 - 6 Floorplan Carelessly control the place and route © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

What the FPGA Editor Cannot Do • The FPGA Editor cannot: – Add additional

What the FPGA Editor Cannot Do • The FPGA Editor cannot: – Add additional logic from a second netlist • • – Make modification to design files • FPGA Editor - 18 - 7 Because translation (NGDBuild) is completed Additional logic would need to be hand-placed and routed HDL and netlist files will not reflect modifications © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Changed notes Removed next slide. • Design Flow Diagram

Rhett Whatcott: v 6. 1: Changed notes Removed next slide. • Design Flow Diagram MAP Xilinx implementation flow – FPGA Editor NCD & PCF Entry points for FPGA Editor PAR • Placing and routing critical components – • Before implementation (Post. MAP) Making minor changes NCD BITGEN BIT – After implementation (Post. Remember to document the changes to your design, PAR) because your netlist will not reflect the changes made by the For Academic Use Only FPGA Editor! FPGA Editor - 18 - 8 © 2003 Xilinx, Inc. All Rights Reserved

Rhett Whatcott: v 6. 1: Removed next two slides. FPGA Editor Push Button Panel

Rhett Whatcott: v 6. 1: Removed next two slides. FPGA Editor Push Button Panel Menu Bar Array Window List Window History Window World Window FPGA Editor - 18 - 9 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: New slide, replacing the next two. • • Navigating

Rhett Whatcott: v 6. 1: New slide, replacing the next two. • • Navigating Zoom • Array window resources Use the World window to keep track of your location on the die when you are zoomed in FPGA Editor - 18 - 10 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: retranslate. • • Easiest way to select objects in

Rhett Whatcott: v 6. 1: retranslate. • • Easiest way to select objects in your design Displays – – – • Components Nets Paths Layers Constraints Macros Name Filter search feature – – • List Window Limit the number of elements shown Use Wildcards (* and ? ) Ability to highlight components – FPGA Editor - 18 - 11 Choose from 15 different colors © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Viewing Device Resources… section moved here. Changed the order

Rhett Whatcott: v 6. 1: Viewing Device Resources… section moved here. Changed the order of the sections. Outline • • • FPGA Editor - 18 - 12 FPGA Editor Basics Viewing Device Resources and Constrained Paths Adding a Probe Making Minor Changes Summary Appendix: Creating a Macro © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Removed previous slide. • • • Select a slice

Rhett Whatcott: v 6. 1: Removed previous slide. • • • Select a slice or IOB Click the editblock button View LUT configuration – – • Viewing the Contents of a Slice or IOB LUT RAM ROM SRL View the LUT equations – FPGA Editor - 18 - 13 Click the Show/Hide Attributes button © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Viewing Constrained Paths • View constraints in the List window – • Perform a

Viewing Constrained Paths • View constraints in the List window – • Perform a timing analysis – • Select Constraints in the pulldown menu Tools Trace Setup and Run Trace window – – – FPGA Editor - 18 - 14 Generates a Timing Analysis report Select the Type of Report Click Apply © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Viewing Constrained Paths • Trace Summary window – – • Select the constraint to

Viewing Constrained Paths • Trace Summary window – – • Select the constraint to report on Click Details The Trace Errors window – – FPGA Editor - 18 - 15 Lists the slack on each delay path Most-critical path is listed last Select a delay path to be displayed Click Hilite © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Moved location of this slide… retranslate. • Calculating Skew

Rhett Whatcott: v 6. 1: Moved location of this slide… retranslate. • Calculating Skew Determine net delays – History window shows: • • • Click the “attrib” button – – • Net destination Associated delay Located on the Push Button Panel Select Pins tab Determine skew – FPGA Editor - 18 - 16 (Longest Delay) - (Shortest Delay) © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Viewing Multiple Windows • Multiple Array windows can be viewed by using the command:

Viewing Multiple Windows • Multiple Array windows can be viewed by using the command: – – • • Window New Array Window List, Array, or World window can be selected Useful for viewing different areas of interest at the same time View and edit the sources and destinations of routes FPGA Editor - 18 - 17 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Changed the order of the sections - moved “Viewing

Rhett Whatcott: v 6. 1: Changed the order of the sections - moved “Viewing Device Resources…” as 2 nd section. Outline • • • FPGA Editor - 18 FPGA Editor Basics Viewing Device Resources and Constrained Paths Adding a Probe Making Minor Changes Summary Appendix: Creating a Macro © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Adding a Probe: Probes GUI • • Ties an internal signal to an output

Adding a Probe: Probes GUI • • Ties an internal signal to an output pin Probes are managed in the Probes GUI – – • Click the “probes” button on the Push Button Panel Tools Probes can be added, deleted, edited, or highlighted FPGA Editor - 18 - 19 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Adding a Probe: Probes GUI • Click the Add button – • • Opens

Adding a Probe: Probes GUI • Click the Add button – • • Opens the Define Probe window Select desired probes to Delete, Edit, or Hilite After a Probe has been added: – – – FPGA Editor - 18 - 20 Click Bitgen to create new bitfile Click Download to open i. MPACT programmer Document the change © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 5. 2: Changed Notes for Demo. Defining a Probe • Enter

Rhett Whatcott: v 5. 2: Changed Notes for Demo. Defining a Probe • Enter a Pin Name Select Net to be probed Click OK • Filter feature to limit net options • Method • • – Automatic routing • • – Manual routing • • FPGA Editor - 18 - 21 Selects the shortest route Possible long wait times Specific pins can be selected Selects the shortest route if multiple pins are selected © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Changed the order of the sections - moved “Viewing

Rhett Whatcott: v 6. 1: Changed the order of the sections - moved “Viewing Device Resources…” as 2 nd section. Outline • • • FPGA Editor - 18 - 22 FPGA Editor Basics Viewing Device Resources and Constrained Paths Adding a Probe Making Minor Changes Summary Appendix: Creating a Macro © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: retranslate. • Adding a Component – – – •

Rhett Whatcott: v 6. 1: retranslate. • Adding a Component – – – • Adding Components Select the resource (slice, IOB, etc. ) from the Array window Click the add button Complete the Component Properties box All resources can be added FPGA Editor - 18 - 23 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: New slide. Adding Component Pins • Adding component pins

Rhett Whatcott: v 6. 1: New slide. Adding Component Pins • Adding component pins – – – Select pin Select “add” in push button panel Complete Properties box • FPGA Editor - 18 - 24 Pin name © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: retranslate. Added demo. • Modifying the equations – –

Rhett Whatcott: v 6. 1: retranslate. Added demo. • Modifying the equations – – Click the Show/Hide Attributes button Complete the Component Properties box • – * (AND), + (OR), ~ (NOT), @ (XOR) Select Apply changes • • Modifying LUTs Tool performs a Design Rule Check (DRC) Click the Save Changes and Close Window button FPGA Editor - 18 - 25 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Added demo. • Add resources – – – •

Rhett Whatcott: v 6. 1: Added demo. • Add resources – – – • Modifying Other Slice Resources Select properties of resource Click on pin to route signal paths This will automatically route the signals inside the slice Click the Apply button – Performs a Design Rule Check Click the Save Changes FPGA Editor - 18 - 26 and Close Window button • © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: New slide. • Routing Signals Routing setup: Tools Route

Rhett Whatcott: v 6. 1: New slide. • Routing Signals Routing setup: Tools Route Auto Route Setup… – Auto Route Design: Options used to auto route the entire design (default values) • • – Timespec Driven: Auto routes signals to meet timing constraints – Generally best results Allow Pin Swap: Allow for pin swapping during auto routing. Enables better use of resources Auto Route Selection: Options used for a selected route (pins, nets, components) • • FPGA Editor - 18 - 27 Delay driven: Auto routes selected item as fast as possible – Generally best results Resource Driven: Minimizes use of resources (wires and pips) during auto route – Default © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: V 6. 1: new slide. Rerouting Signals Auto Routing • Rerouting a

Rhett Whatcott: V 6. 1: new slide. Rerouting Signals Auto Routing • Rerouting a signal: – – FPGA Editor - 18 - 28 Select net in Array or List window to reroute Click unroute in pushbutton panel Specify routing options (Auto Route Setup) Click autoroute in pushbutton panel © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Changed Heading. Manual Routing Signals I • Select site

Rhett Whatcott: v 6. 1: Changed Heading. Manual Routing Signals I • Select site pins – – – • Route the net – • Click the site pin of a resource Hold down the Shift key Click another site pin Click the “route” button Automatically chooses the shortest route between site pins FPGA Editor - 18 - 29 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Changed Heading. Manual Routing Signals II • Select object

Rhett Whatcott: v 6. 1: Changed Heading. Manual Routing Signals II • Select object to route – – • Route the net – • Click the site pin of a resource Hold down the Shift key Click net Click subsequent nets Click the “route” button Routes one net segment FPGA Editor - 18 - 30 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Changed Heading. Manual Routing Signals III • Select object

Rhett Whatcott: v 6. 1: Changed Heading. Manual Routing Signals III • Select object to route – – – • Route the net – • Click previously routed segment Hold down the Shift key Click site pin Click the “route” button Automatically chooses the shortest route from segment to site pins FPGA Editor - 18 - 31 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: retranslate. Adding an External IOB • Adding an IOB

Rhett Whatcott: v 6. 1: retranslate. Adding an External IOB • Adding an IOB – Select IOB • – – • Make certain the IOB is bonded, unbonded IOBs have X in IOB box Select “add” in pushbutton panel Edit Properties, click OK Use the editblock command to edit resources FPGA Editor - 18 - 32 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Changed heading. Removed next slide. • IOB Resources Input/Output

Rhett Whatcott: v 6. 1: Changed heading. Removed next slide. • IOB Resources Input/Output registers, output 3 -state, I/O standard, drive strength, and slew rate control can be viewed and modified FPGA Editor - 18 - 33 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Rhett Whatcott: v 6. 1: Changed the order of the sections - moved “Viewing

Rhett Whatcott: v 6. 1: Changed the order of the sections - moved “Viewing Device Resources…” as 2 nd section. Outline • • • FPGA Editor - 18 - 34 FPGA Editor Basics Viewing Device Resources and Constrained Paths Adding a Probe Making Minor Changes Summary Appendix: Creating a Macro © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Review Questions • List some of the common uses for the FPGA Editor •

Review Questions • List some of the common uses for the FPGA Editor • When should the FPGA Editor not be used? • What are the benefits of inserting a probe? • If any modifications were made using the FPGA Editor, it is important to _____ any changes. Why? FPGA Editor - 18 - 35 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Answers • List some of the common uses for the FPGA Editor – –

Answers • List some of the common uses for the FPGA Editor – – • View device resources Make minor modification Insert probes Generate a new bitstream When should the FPGA Editor not be used? – FPGA Editor - 18 - 36 FPGA Editor should not be used to Floorplan a design or control the place and route © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Answers • What are the benefits of inserting a probe? – • The probes

Answers • What are the benefits of inserting a probe? – • The probes capability makes it possible to route a signal to an output pin for testing, and generate a new bitstream for the design without re-implementing If any modifications were made using the FPGA Editor, it is important to Document any changes. Why? – FPGA Editor - 18 - 37 It is necessary to document your changes because the netlist will not reflect the changes made by the FPGA Editor © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Summary • • • The FPGA Editor provides you with a tremendous amount of

Summary • • • The FPGA Editor provides you with a tremendous amount of design control Most customers use this tool for understanding the device utilization or adding test probes Careful use of this tool is important because indiscriminate movement of logic can severely reduce the likelihood of getting good design performance and utilization The FPGA Editor allows you to make minor changes to a design without re-implementing your design Document any changes to your design because your netlist will not reflect the changes made by the FPGA Editor - 18 - 38 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

Where Can I Learn More? • FPGA Editor Help – – • http: //support.

Where Can I Learn More? • FPGA Editor Help – – • http: //support. xilinx. com Software Manuals Help Topics Tech Tips – FPGA Editor - 18 - 39 http: //support. xilinx. com Tech Tips Floorplanner & FPGA Editor © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only