Programmable Logic Devices Introduction Fixed Function ICs They

Programmable Logic Devices

Introduction • Fixed Function ICs§ They perform a specific, fixed function § They are designed by manufacturers in large quantities § Eg. - multiplexers, adders, comparators etc. • § § § Advantages: Low development cost Fast turn around of designs Relatively easy to test the circuits

• § § Disadvantages: Large board space requirements Large power requirements Lack of security Additional cost, space, power requirements etc. to modify the design or to introduce more features

ASICs (Application specific integrated circuits) § They overcome the disadvantages of fixed function ICs § They are designed by the users according to the user’s specifications and are produced by the IC manufacturer as per the user’s specifications § Ø Ø Ø Advantages of ASICs: Reduced space requirements Reduced power requirements Cost is reduced considerably when produced in large volumes Large reduction in size through use of high level of integration Very difficult to copy the designs § Disadvantages of ASICs: Ø Enormous initial development cost Ø Testing methods needs to be developed which may increase the cost

Programmable Logic Devices (PLDs) • They have the advantage of fixed ICs as well as ASICs. • PLD is an IC that is user configurable and is capable of implementing logic functions • It is a VLSI chip that contains ‘regular’ structure and the designer can customize it for specific application. • They have short design cycle and low development cost as in fixed function ICs • They have higher density, lower quantity production costs, design security, reduced power and space requirements as in ASICs

• § § § Advantages of PLDs over fixed function ICs Reduction in board space requirements Reduction in power requirements Design security Compact circuitry Higher switching speed

• Various PLDS: Ø ROMs Ø PLA Ø PAL Ø SPLDs Ø CPLDs Ø FPGA

ROM as a PLD • It is a combinational circuit used to implement a logic function • A ROM of size M X N has M locations and N number of bits can be stored at each location • Number of address inputs is ‘P’ where • A ‘P’ variable function, with ‘N’ outputs logic fn can be implemented using ROM of size • In case of PROM, EPROM, and E 2 PROM user can program them • Since programmable ROMs can be used for logic design it is also referred to as PLD

Advantages of using ROM as a PLD • Easy to design since there is no need of simplification or minimization of logic function • Designs can be changed or modified rapidly • Usually faster than discrete SSI/MSI • Cost is reduced • • Disadvantages of ROM-based circuits: Non-utilization of complete circuit Increased power requirement Enormous increase in size with increase in input variable

PLDs- PAL & PLA • PLD consists of programmable array of logic gates and interconnections • The logic gates may be two level AND-OR, NAND, NOR-NOR configuration or sometimes AND-OR-EX-OR configuration • There are two typed of PLDSØ PLA Ø PAL They are suitable for implementing logic functions in SOP form

PLA- Programmable Logic Array • Consists of two level AND-OR circuits on a single chip • The number of AND, OR gates and inputs are fixed • It has M inputs, n product terms, and N outputs with and can be used to implements a logic function of M variables with N outputs • All of the possible minterms are not available, hence logic minimization is required to accommodate the given logic function

Block diagram of PLA device

• 1. Input Buffer • Buffer circuits are required to limit loading of the sources that drive the inputs • It produces inverted and non-inverted inputs at the output for one input • Similar buffers are there for each of the M inputs

AND Matrix • Used to form product terms • Each AND gate has all the input variables in complemented and uncomplemented form • There is a nichrome fuse link in series with each diode • All the links are intact in unprogrammed PLA device

• Each AND gate generates one product terms given by: P= I 0. I 1. …IM-1. I M-1 It is logic 0 in unprogrammed device • To generate required product term unwanted links are opened

Section of AND matrix for P 0 output and its equivalent logic gate representation

• This is a convenient method to show the input buffers and the AND matrix with interconnections marked as ‘X’. When an array is programmed to implement a function the desired interconnections are left with ‘X’ marks and the unwanted interconnections without ‘X’ marks

OR Matrix • Consists of parallel connected transistors with common emitter load. Outputs are obtained at S 0 through SN-1 • When all the fuse links are intact output S 0 is given by S 0 = P 0 + P 1+…. + Pn-1 • Required sum terms are generated by opening the unwanted fuse links, which effectively makes logic level 0 at the corresponding OR gate inputs

OR Matrix Logic Symbol of a Section of OR matrix Representation of OR Matrix

Invert/Non-Invert matrix • It is a programmable buffer that can be set for inverting or non-inverting operation corresponding to active low or active high S output respectively • In case of EX-OR gate, if the fuse is intact, the output is ‘S’ but if the fuse is blown off, the output is S bar

Output Buffer • They are used to increase the driving capability of PLA. • The outputs may be totem pole, open collector, or three state, but generally they are TTL compatible.

Applications Of PLA • To implement combinational and sequential logic circuits • Procedure to implement combinational logic functions are: 1. Prepare truth table 2. Write the Boolean equations in SOP form 3. Simplify the equations to obtain minimum SOP form. ( main criteria is to minimize the number of product terms) 4. Determine the input connections of AND matrix to generate the required product terms 5. Determine the input connections of OR matrix to generate the required sum terms 6. Determine the connections required for invert/non-invert matrix to set the active logic levels of the outputs. 7. Program the PLA

PAL-Programmable Array Logic • As compared to PLA, PAL has programmable AND array and a fixed OR array in which each OR gate gets inputs from some of the AND gates. ie. . All the AND gate outputs are not connected to any OR gate

• It has 5 inputs, 8 programmable AND gates, and 4 fixed OR gates • The input and output circuits of PALs are similar to those of PLAs. • The number of fusible links in a PAL is the product of 2 M and n, where M is the number of input variables and n is the number of product terms. • Limited number of product terms are available for each output. Hence logic minimization techniques are required when logic circuits are implemented in PAL devices

CPLDs- Complex Programmable Logic Devices • SPLDs such as PALs etc. have limited number of inputs, product terms and outputs • To implement circuits with more inputs and outputs than that are available in a single chip, we can use multiple SPLDs or CPLD. • But using multiple SPLDs have some disadvantages

• A CPLD is a collection of individual PLDs on a single chip and programmable interconnection structure • CPLDs are manufactured by different manufacturers. Eg. XC 9500 by Xilinx

• Consists of PAL-like blocks, I/O blocks and a set of interconnection wires. • PAL-like blocks are connected to a set of interconnection wires and each block is also connected to an I/O block to which chip’s inputs and output pins are attached • PAL like block usually consists of 16 macrocells. • Each macrocell consists of an AND-OR configuration, an EX-OR gate, a flipflop, a mux, and a tristate buffer

• Each AND-OR configuration usually consists of 5 -20 AND gates and an OR gate with 5 -20 inputs. • EX-OR gate is used to obtain the output of OR gate in inverted or non-inverted form • A D FF stores the output of the EX-OR gate • A mux selects either the output of the D FF or the output of the EX-OR gate depending upon its select input • The tri state buffer acts as a switch which enables the chip’s pin to be used either as an output (tri-state enabled) or as an input (tristate disabled)

Block Diagram of CPLD

Microcell

Field Programmable Gate Array (FPGA) • CPLDs and SPLDs have basic architecture- that of PAL or PLA • To increase the effective size and to add more functionality in a single programmable device , FPGA has been developed. • Its logic density is higher than that of CPLD ( ranging from few thousands to hundreds of thousands equivalent gates) • Large complex circuits can be implemented on FPGA • Eg. Spartan from Xilinx.

FPGA Block diagram

Block Diagram- Explanation • It consists of CLBs (configurable logic blocks)- are organized as an array of rows and columns • The logic blocks are connected to the I/O blocks through common row/column programmable interconnects • The row/column interconnects are known as global interconnects • A logic block consists of number of logic modules (LMs) • The logic modules are the basic logic elements in an FPGA • The logic modules within a CLB are connected through local programmable interconnects