Extending Atmel FPGA Flow Nikos Andrikos TECEDM ESTEC

Extending Atmel FPGA Flow Nikos Andrikos TEC-EDM, ESTEC, ESA, Netherlands DAUIN, Politecnico di Torino, Italy NPI Final Presentation 25 January 2013 - ESTEC 1

Making Atmel FPGA Flow Work Nikos Andrikos TEC-EDM, ESTEC, ESA, Netherlands DAUIN, Politecnico di Torino, Italy NPI Final Presentation 25 January 2013 - ESTEC 2

Outline • Introduction • FPGAs in Space • Atmel FPGAs • Atmel IDS • Methodology • Results • Conclusion 3

Field Programmable Gate Arrays • General purpose configurable circuits o Compared to Application-Specific Integrated Circuits (ASICs) • Pros o Rapid prototyping o Fixed cost per unit o Reprogrammability • Cons o Lower performance o Higher power consumption 4

FPGAs in Space • Aforementioned advantages o Increased momentun in their usage in space • Electronic circuits subject to radiation o Need for radiation hardening • ITAR regulations o Increased bureaucracy o Preventing export to embargoed countries (e. g. China) 5

Atmel FPGAs • The only FPGA option that is o RAD-hard o ITAR-free c. Suitable for ESA applications • Many technologies available o 180 nm AT 58 KRHA 180 nm CMOS ATF 280 Family (used in this project) o AT 40 KEL 040 350 nm CMOS o ATFS 450 150 nm SOI Available in the future 6

Atmel IDS • Atmel Integrated Development Systems (IDS) o Default software to program Atmel FPGAs o Provided by Atmel • But, o Has not been significantly updated recently o Usability issues o Obsolete algorithms c. Leaves much to be desired 7

IDS Examples 8

Outline • Introduction • Methodology • • • Scope of the work Default flow Proposed flow VPLACE Experimental Setup • Results • Conclusion 9

Scope of Work • Improve IDS flow o Usability issues o Explore various implementation options • Try alternative algorithms o VPLACE for placement • Quantative evaluation o Use of various designs o Comparison between default IDS and VPLACE algorithms 10

Default Flow • Hardware specification o Hardware Description Language (HDL) • Mentor Precision o Logic Synthesis • Atmel IDS o o 11 Technology mapping Placement Routing Bitstream Generation HDL Mentor Precision Logic Synthesis Netlist Atmel IDS Tech Mapping Placement Routing Bitstream

Proposed Flow • Automate the flow o o Mentor Precision Makefile usage Constraint generation Tool invocation Optimize IDS options • Replace IDS placement o Parse project DB o VPLACE placement o Update project DB 12 HDL Logic Synthesis Netlist VPLACE Atmel IDS DB Parse Placement DB Update Tech Mapping Project DB Placement Routing Bitstream

VPLACE • Academic algorithm for FPGA placement o Previously developed in Politecnico di Torino, Italy o Already used for Xilinx FPGAs • Algorithm still not optimized for Atmel o Not timing-driven o Not tuned for Atmel architectures o But, already promising results • Project database (DB) interface o Specifically developed during this project o Reverse-engineering of Atmel DB format (. fgd) o Around 3 K C++ lines of code 13

Experimental Setup • Compare the two flows o Implementation targeting ATF 280 FPGA family o IDS vs VPLACE placement o Compare performance (circuit period) • Use of designs of interest o ITC ‘ 99 benchmarks (initial verification) o Hurri. CANe 5. 2. 4 (CAN bus) o Crf 0. 90 (by Astrium Crisa) 14

Outline • Introduction • Methodology • Results • ITC/Hurri. CANe • CRF • Conclusion 15

Results 1/2 Design Hurri. CANe 91. 6 VPLACE Diff % 89. 6 -2. 2 Design 30. 1 226. 5 b 10 IDS VPLACE Diff % 20. 8 27. 9 34. 1 b 01 9. 2 b 02 7. 2 9. 0 24. 6 b 11 35. 1 - N/A b 03 21. 4 31. 7 48. 5 b 12 57. 5 54. 5 -5. 5 b 04 43. 5 42. 7 -1. 9 b 13 24. 1 27. 1 12. 7 b 05 45. 1 44. 1 -2. 4 b 14 156. 4 148. 8 -4. 8 b 06 9. 0 17. 4 93. 8 b 14_1 161. 4 160. 4 -0. 6 b 07 24. 7 30. 2 22. 2 b 15 115. 9 115. 8 -0. 0 b 08 34. 2 39. 2 14. 7 b 15_1 114. 8 120. 5 5. 0 b 09 16 IDS 28. 5 33. 5 Critical Period (ns) 17. 4 b 17 134. 4 151. 0 12. 39 Critical Period (ns)

Results 2/2 • Compare critical period of two runs o Different placement algorithms o VPLACE vs default IDS • IDS pushed to maximum effort o Enabled timing-driven optimizations • VPLACE still not optimized o Much way to go Route congestion Suboptimal results o But, already some improvement 17 Up to 5% for some ITC benchmarks 2. 2% better for Hurri. CANe

CRF Results • Design by Astrium Crisa o Contact made during latest SEFUW (Nov 2012) o Provided only synthesized netlist Flow does not necessarily need RTL anyway o Targeting AT 40 KEL 040 family • Desired frequency of 10 MHz o Crisa’s implementation had reached 4 MHz o Our flow reached 9. 6 MHz (2. 4 x speedup)! Just by using our default IDS flow VPLACE does not support inout ports 18

Conclusions • Fully automated Atmel FPGA flow o More user friendly Only few lines of configuration needed for each project o Unattended runs o Fast constraints exploration o Fine tuning of IDS options Better results even than industrial attempts • VPLACE algorithm o Alternative to default IDS placement o Still not optimized for Atmel Not timing-driven Not tuned for Atmel architecture 19 o But, some promising results already

Future Work • Wait for newer version of VPLACE • Try additional designs o Space. Wire o Other you suggest? • Further exploration of IDS configuration options 20

Thanks! Questions? nikos. andrikos@esa. int www. esa. int/TEC/Microelectronics/ 21