Alteras Innovative Intellectual Property IP Overview 2008 Altera

Altera’s Innovative Intellectual Property (IP) Overview © 2008 Altera Corporation—Public

The Programmable Solutions Company® Intellectual property (IP) Programmable logic devices (PLDs) and ASICs A key enabler for the devices © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 2

FPGA Trends—System Interconnect FPGA µP I/O IP Memory ASSP 1. Standard I/O protocols for easy connection to other chips © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 3

FPGA Trends—Embedded Processing FPGA µP µP I/O IP Memory DSP processor ASSP 2. Embedded µP and digital signal processing (DSP) blocks for processing and coprocessing © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 4

FPGA Trends—System Integration Need to reduce board size to meet form factor requirements Too expensive: need to reduce cost I/O Flash Obsolete in 2 years and must support for 7 years CPU Changing standard requires new device: redesign board Marketing requires new features to stay competitive SDRAM I/O I/O I/O DSP FPGA CPU DSP CPU 3. Replace external devices with programmable logic © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 5 16 -week lead time must qualify 2 nd source

Altera IP Solutions Strategy n Focus in-house development on: - High-speed I/O interconnect technologies l PCI Express, Serial Rapid. IO® standard, Ethernet, Serial. Lite II, memory controllers - DSP applications l Video and image processing and general purpose - Embedded market l Nios® II embedded processors, peripherals, and design environment n Leverage third-party partners for additional products and expertise n Complete solutions - Flexible, high-quality IP cores - Proven validation using development kits - Reference designs to kick-start system design n Interoperability testing for key I/O protocols © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 6

Altera IP Portfolio* Processors and peripherals n 32/16 bit - Nios II embedded processor DSP n - Finite impulse response (FIR) - Fast Fourier transform (FFT) - Cascaded integrator comb (CIC) n SOPC Builder peripherals n - SDRAM - Flash - UART n Modulation and demodulation - Numerically controlled oscillator - Serial peripheral interface (SPI) - Programmable I/O Error correction and detection - Viterbi - Reed-Solomon - Turbo - SRAM - Timer Filters and transforms (NCO) - Digital video broadcast (DVB) n Video and image processing - H. 264 decoder - JPEG encoder/decoders * Includes partner IP © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 7 - MPEG 2/4 CODECs Color space converter Scaler 2 D FIR filter 2 D median filter Line buffer compiler Gamma corrector Chroma resampler Deinterlacer Alpha blending mixer Clocked video input Clocked video output Frame buffer Clipper Color frame sequencer

Altera IP Portfolio* (Continued) Memory and memory controllers Interface protocols n Communications n - Packet over SONET (POS) PHY 2/3 and SPI 4. 2 - 8 B / 10 B - Utopia - Cyclical redundancy check (CRC) n media access control (MAC) and physical coding sublayer (PCS) - 10 -Gbps MAC and PCS - 1588 industrial Ethernet - Any speed MAC n - Rapid. IO standard - Hyper. Transport™ technology - Serial. Lite II n PCI n n Serial - USB 2. 0 function - I 2 C n Direct memory access (DMA) - DMA controller - Scatter gather DMA - 32 -/64 -bit PCI - PCI-X - PCI Express /1, /4, /8 Ethernet - 10/1000 Mbps High speed Video - Serial digital interface (SDI) - Asynchronous serial interface (ASI) * Includes partner IP © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 8 SDRAM - DDR / DDR 2 SDRAM controllers - DDR / DDR 2 / DDR 3 SDRAM highperformance controllers - RLDRAMII controller - QDR II controller

PCIe Hard IP - Value Proposition n n FPGA industry’s 1 st 40 -nm FPGA with PCI Express Gen 2 support Cost - ~0 LEs used - $0 list price n Ease of use - No separate licensing required - Significantly reduced compile times l Equivalent to ~12 K – ~20 K LEs l Exact numbers available at customer beta - Significant power savings as compared to soft IP solution n Low risk - 2 nd generation FPGA with PCIe Gen 2 support - 4 th generation FPGA with support for PCIe © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 9

Complete Solutions Intellectual property (IP) n n n Encrypted source code Testbench Documentation Software tools n n n Reference designs and design examples Development kits © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 10 Quartus® II software SOPC Builder DSP Builder

World-Class Third-Party IP Partners © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 11

System Integration Create design blocks Integrate system Model-based design IP ‘C’-based design entity par_fir is port ( io 0_gpo : out std_logic_vector(15 downto 0); io 0_gpi : in std_logic_vector(15 downto 0); clock : in std_logic; reset : in std_logic ); end entity; HDL Entry Embedded software development © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 12 Including

Altera Development Kits n Focus on quality and completeness - All boards are fully tested and verified before shipment - Accompanied by accurate technical documentation n Complete design environment - Board with featured Altera® device - Quartus II software (development kit edition) - Altera IP library for free hardware evaluation - Kit CD with reference designs and utilities - Documentation - Schematics/board layout files - Cables and accessories as necessary © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 13 It’s in the box!

Ease of Use © 2008 Altera Corporation—Public

Customer Expectations from IP n Works functionally n Meets performance requirements in real designs n Area-efficient n Other deliverables - Quality documentation - Example design - Test bench - Software drivers and protocol stacks - Simulation models - Hardware test platform n Quality support © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 15 FPGA IP

Altera IP n Optimized for latest device families n Easier migration across device families via cross-platform support n VHDL and Verilog support n Intuitive, easy-to-use GUI for core configuration/parameterization n Shares release schedule with Quartus II software © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 16

Interoperability Is Required n Proactive I/O protocol compliance and interoperability testing - PCI Express - Ethernet - Serial Rapid. IO (SRIO) standard n Interoperability at industry-standard forums - PCI-SIG-compliance workshops - Ethernet University of New Hampshire (UNH) validation - Lab testing for Rapid. IO standard n Additional interoperability with ASSP, DSP, and processor devices - PCI Express, SRIO switches - DSP processors © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 17

Typical IP Costs Planning Register transfer level (RTL) coding Verification Enhancements* Documentation Hardware platform Hardware testing GUI Total cost: $1. 1 M Time to develop: 1 to 1. 5 years QA Release Marketing * Yearly costs © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 18 0 K $3 5 0 K $3 0 0 K $2 5 0 K $2 0 0 K $1 5 0 K $1 0 K $5 0 $0 K Support

Altera’s Investment in IP n Geographically dispersed organization Marketing - Centers of expertise (UK, San Jose, Santa Cruz, and Penang) n > 154 staff members Support Engineering (new) - IP development engineers - Software engineers - Technical writers - Quality assurance and training - Infrastructure and packaging tools - Application support engineers - Product planning - Product marketing n Documentation Software tools Nios II embedded processor engineering Annual spending is ~9% of R&D © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 19 Engineering (maintenance)

Worldwide IP Centers San Jose, CA Santa Cruz, CA High Wycombe, UK Penang, Malaysia • • • Nios II embedded processor • Nios C-to-H Compiler (C 2 H) • DSP • System solution engineering • Ethernet • PCI • Memory controllers PCI Express Rapid. IO standard Serial. Lite II QA © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 20

Application Examples © 2008 Altera Corporation—Public

DSP in FPGA: Video Conferencing Video Audio Deinterlacer Spatial noise reduction Audio CODEC CSC Scaler Audio mixing Multichannel audio decode Alpha blending for OSD PIP mixer Polycom VXS 8000 Altera IP 3 rd-party or customer-proprietary IP DSP © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 22 ENCODER Encoder TCP/IP stack Multichannel decode Network

DSP in FPGA: Wireless Basestation Power amplifier (PA) Low-noise amplifier (LNA) A/D D/A Digital I/F DUC/DDC DPD CFR Baseband processing Rel 6/LTE/Wi. MAX Glue logic RF card Host CPU Control logic Multiplexer/ demultiplexer Host µP IP proc Channel card Clock generator Switch I/F GPS receiver IP/ATM interface Glue logic Control card Timing card Switch card Altera FPGA applications © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 23 BSC/RNC interface

Gigabit Ethernet in FPGA: Multi-Port Switches n Flexible Altera Ethernet solution - Target MAC for both transceiver and non-transceiver FPGAs - Triple-speed operation (10/1000 Mbps) with auto-negotiation ensures smooth data rate upgrades 10/100 MAC Gigabit MAC Switch core Atlantic interface MI /GMII or SGMII Atlantic™ interface 10/100 MAC 10 / 1000 MAC Altera IP 3 rd-party or customer-proprietary IP Content courtesy of IP partner: More. Than. IP © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 24 Serial peripheral interface (SPI) 4. 2 master

10 -Gigabit Ethernet in FPGA Line-Side Application XFI XFP Gb. E MAC 10 -Gb. E MAC XFP XAUI XCVR Gb. E MAC SFP SFP SFP Altera IP n 3 rd-party or customer-proprietary IP High-end server add-in cards - Examples: multi-source data capture, TCP/IP offload, pre-buffering, custom processing, redundant XAUI ports Data plane endpoint n Backplane interconnect n High-end performance n Content courtesy of IP partner – More. Than. IP, Altera preferred partner for 10 G MAC © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 25

PCI Express in FPGA Endpoints, Bridges, and Switches n PCIe x 4 Endpoints - Memory controller - Gigabit Ethernet (Gb. E), Fibre Channel, etc. - Proprietary n Non-transparent bridge - PCI, PCI-X n PHY x 4 Memory Non-transparent switch PCI - Avalon® interface PHY x 1 PCIe x 4 PHY PCIe x 1 Avalon bridge Avalon Gb. E MAC PCI Memory controller PCIe x 1 Legacy ASSP XXXXXXX Avalon bridge Legacy ASSP Altera IP © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 26

Serial Rapid. IO Standard in FPGA Bridges and Custom Endpoints CPRI, PCI Express, Ethernet Serial Rapid. IO standard n Bridges - PCI, PCI Express, Common Public Radio Interface (CPRI), Open Base Station Architecture Initiative (OBSAI), Ethernet, etc. Memory n Custom endpoints - Nios® II control plane CPU SRIO switch DSP ASSP processing © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 27

Serial Rapid. IO Standard in FPGA (2) Multiprocessing System n FPGA-based switch fabric DSP SRIO switch DSP © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 28

Embedded Design with Nios II Embedded Processor n Processing power is ideal for: - Automotive - Industrial - Access communications © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 29

Getting Started © 2008 Altera Corporation—Public

Core Delivery n Delivered and installed as part of Quartus II software beginning with v 8. 0 release n Web download from www. altera. com - Included with both Subscription and Web Edition versions of Quartus II software n After installation, cores can be selected within Quartus II software and SOPC Builder n 3 rd-party IP is delivered upon request by Altera partners - Web product page has automated request form © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 31

IP Deployment Flow Parameterize Real-time logic simulation W eb Install VHDL and Verilog Altera IP design flow © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 32 Hardware evaluation

Licensing Altera IP n Perpetual-use licenses for production designs - Royalty-free license grant - One-year renewable maintenance, upgrades, and support - Floating or node-locked licenses - Migrate to Altera Hard. Copy® devices for no additional fee n Corporate and site licenses can be established to meet an individual company’s needs © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 33

Summary n Altera development is focused on: - High-speed I/O interconnect - DSP - Embedded technologies n n Altera invests in producing complete, easy-to-use solutions 3 rd-party partner products expand Altera portfolio and expertise Enabling faster time-to-market © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 34