Why Youll Want to Think Altera When You

Why You’ll Want to Think Altera When You Think About Your Next Embedded System © 2008 Altera Corporation—Public

Agenda n Why developers choose Nios® II processors n Nios II Embedded Evaluation Kit (NEEK) demo— a real example n Nios II performance n System integration using Altera® embedded technology n Resources available n Conclusion © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 2

Estimated FPGA/PLD Design Starts, Worldwide, 1999 -2011 100, 000 102, 000 107, 100 80, 000 100, 010 94, 248 90, 125 92, 378 87, 756 84, 823 84, 102 85, 532 80, 582 83, 000 95, 704 60, 000 40, 000 20, 000 With microprocessor core Without microprocessor core n There are more soft cores than hard cores in the FPGA market n Gartner believes that Altera is shipping the most soft processor cores in FPGAs (Nios processor and, more recently, ARM®) Source: Gartner Dataquest © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 3

Why Developers Choose Nios II Processors n Custom fit to users’ application n Works with all Altera FPGA devices n Scalable performance n Concept to system in minutes © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 4

Nios II Processor - World’s Most Popular Soft Processor n Over 20, 000 development kits shipped - Used in communications, consumer, industrial, medical, automotive, and broadcast products worldwide - Used by all of the top 20 OEMs n Active Nios design community (www. niosforum. org) - Over 8, 000 active members © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 5

Nios II Embedded Evaluation Kit (NEEK): A Real Example © 2008 Altera Corporation—Public

Nios II Evaluation Kit - Hardware Only USD $449 n n n Cyclone® III EP 3 C 25 FPGA Drop-in design examples included on SD card Great out-of-box experience for software developers © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 7

Nios II Evaluation Kit - Hardware Only USD $449 n Cyclone III starter board - EP 3 C 25 FPGA - 32 -MByte DDR - 1 -MByte SSRAM - 16 -MByte flash - USB-Blaster™ circuitry - JTAG header - HSMC connector © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 8

Nios II Evaluation Kit - Hardware Only USD $449 n Multimedia board - Color touch-panel LCD - 800 x 480 resolution - Composite video input - VGA output - Audio input - Microphone input - Audio output - SD card I/F - 10/100 Ethernet (PHY) - PS 2 - RS-232 © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 9

Nios II Performance © 2008 Altera Corporation—Public

Performance Range 300 Performance (DMIPS*) 250 MIPS 200 150 100 MIPS 50 MIPS 0 Nios II/e processor Nios II/s processor * Dhrystone 2. 1 Benchmark © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 11 Nios II/f processor

Nios II Processor Performance (DMIPS) Nios II/f processor Nios II/s processor Nios II/e processor Stratix® III FPGA 300 128 50 Stratix II FPGA 251 110 44 Stratix FPGA 168 82 27 Hardcopy® Stratix II device 228 129 49 Hardcopy Stratix device 166 84 27 Cyclone III FPGA 165 68 17 Cyclone II FPGA 144 55 18 Cyclone FPGA 130 53 17 Device family © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 12

3 Ways to Scale Performance Multi-processor system FPGA CPU External CPU or DSP PCI CPU Custom instructions FPGA CPU Custom instructions Hardware accelerators FPGA CPU Hardware accelerator n Add processors (internal and/or external) n Accelerate individual CPU performance (add applicationspecific instructions) © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 13 n Accelerate data transformation algorithms with application-specific hardware

Custom Instructions n Extends CPU performance - CPU fetches data, stores results - Ideal for math and logical operations l e. g. , floating point, bit manipulation Iterations/second - Hardware much faster than software Custom logic 120 100 A 80 60 27 X faster 40 20 0 << >> B Software only Custom instruction +Out & Nios II embedded processor * Example: CRC 64 -KByte buffer © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 14

Hardware Accelerators n Concurrent data coprocessing - CPU starts/stops the coprocessor - Coprocessor fetches data and stores results - CPU runs application code concurrently Iterations/second - Ideal for block data operations CPU CRC coprocessor 2, 500 2, 000 1, 500 530 X faster 1, 000 5, 000 0 Software only Custom Coprocessor instruction Arbiter Program Data memory * Example: CRC 64 -KByte buffer © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 15 Arbiter Data memory

Nios II C-to-Hardware Acceleration Compiler n n Automates creation and integration of hardware accelerators Intuitive user interface streamlines C acceleration Uses familiar Nios II IDE Support for standard ANSI C language Right-click to accelerate © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 16

C-to-Hardware Acceleration main () { …variable declarations… init(); while (!error && got_data()) { do_user_interface(); gather_statistics(); if (got_new_data()) d_transform(in_buf, out_buf); check_for_errors(); } cleanup(); } © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 17 Execution time

Right-Click to Accelerate Function main () { …variable declarations… init(); while (!error && got_data()) { do_user_interface(); gather_statistics(); if (got_new_data()) d_transform(in_buf, out_buf); d_transform check_for_errors(); } cleanup(); } © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 18 Execution time

Accelerate Only What’s Needed µP Tasks Nios II processor Accelerator 0% 100% Time budget Nios II MHz Transfer processing from CPU to hardware (95 -MHz Nios processor with C 2 H Accelerator performs image rotation as fast as 1. 4 GHz processor) © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 19

Nios II Processor - Leading the Industry High performance § Multi-processor § Hardware acceleration § Custom instructions Greatest flexibility § Processors § Peripherals § Optimized interconnect Powerful design tools Fastest time to market § On-chip processor debug § Signal. Tap® II logic analyzer § Real-time trace capability § Automated system generation § Hardware/software balance § Fast prototype production © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 20

System Integration Using Altera Embedded Technology © 2008 Altera Corporation—Public

Overcome System Design Challenges Too expensive, need to reduce cost I/O Changing standard requires new device, redesign board I/O Flash CPU SDRAM I/O I/O Marketing requires new features to stay competitive Obsolete in 2 years, must support for 7 I/O DSP FPGA CPU DSP CPU Need to reduce board size to meet form factor requirements © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 22 16 -week lead time, must qualify 2 nd source

System Design Challenges Flash I/O CPU SDRAM I/O I/O DSP FPGA I/O CPU DSP CPU Solution: integrate external devices within programmable device © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 23

System-Level Integration Flash FPGA SDRAM © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 24

First Step in System Design © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 25

SOPC Builder – System Generation Tool Generalpurpose processor UART Ethernet Bus I/F Custom PCI UART ASSP System Device RAM SPI Custom microcontroller Bridge PCI SPI SPI+ UART Custom Generalpurpose processor Companion chip © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 26 Bus I/F Generalpurpose processor Bus I/F PCI Ethernet UART Custom Multi-processor

SOPC Builder System Design 1. Select and configure IP 2. Select connections 3. Generate system HDL simulator FPGA Cuts weeks off development time © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 27

Building a SOPC System Nios II Processor Instruction _Master Data _Master SDRAM ETHERNET_MAC DMA _Master Igor_the _Slave Onchip_ Memory DMA Read Write _ Master _Master UART Control port slave TIMER GPIO SOPC Builder automatically generates system interconnect fabric © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 28

Demo – SOPC Builder n Goal (in 10 minutes) - Show easy it is to build a system with SOPC Builder - Show easy it is to add a custom component to your system n Overview - Using SOPC Builder, we will build a system from scratch. The system will include a processor, memory, Ethernet, and USB n Basic steps 1. Create a new Quartus II project 2. Create a new SOPC-based system 3. Add a Nios II processor to system (repeat for memory, Ethernet) 4. Add custom component – USB 5. View generated system in Quartus II software © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 29

Resources Available © 2008 Altera Corporation—Public

Nios II Embedded Design Suite IDE Integrated software development: manage, build, debug Embedded Design Suite Command linebased software build flow HAL API Peripheral drivers and run-time software library GNU tools debugger, C/C++Compiler © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 31

Nios II Embedded Design Suite Real-time operating system from Micrium* Advanced debugging tools from FS 2 and Lauterbach* Commercial-grade network stack from Interniche* C to Hardware (C 2 H) Compiler* * Full evaluation included in kit &/or web download - license sold separately © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 32

Nios II Hardware Abstraction Layer (HAL) The HAL provides a simple device driver interface to communicate with hardware n HAL benefits - Change your hardware without having to change your software code - When hardware is generated, a matching custom software BSP is created automatically HAL API User program Shared library HAL API Device driver … Device driver Nios II processor system hardware _exit() closedir() fstat() getpid() gettimeofday() ioctl() isatty() kill() lseek() © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 33 open() opendir read() readdir() rewinddir() sbrk() settimeofday() stat() usleep() wait() write()

Operating Systems OS Nios II IDE Plug-In Real time Type e. Cos - Open source Euros RTOS - Commercial Erika Enterprise Commercial Thread. X Commercial Mentor Graphics® Nucleus Plus - Commercial Micrium Micro. C/OS-II Commercial Microtronix µCLinux - Open source Segger emb. OS - Commercial Vector os. CAN - Commercial Community Supported (www. niosforum. org) µCLinux - Open source Company name e. Cos. Centric Euros Evidence Express Logic n For more information go to Operating Systems under www. altera. com. cn/embedded © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 34

Nios II Technical Documentation n Extensive literature section on Altera. com - n Nios II processor design examples - n Nios II Software Developer’s Handbook Nios II Processor Reference Handbook Tutorials Application notes Ethernet Multiprocessor PLL tuning Web server and many more Nios forum (www. niosforum. com) - 7000+ registered Nios II users - Over 5, 800 topics n Nios Wiki (nioswiki. jot. com) - Nearly 100 pages of Nios II user-generated documentation © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 35

Partner Software Development Tools Optimizing C Compiler Nucleus RTOS © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 36

Conclusion n Developers choose Nios II processors because of customization, flexibility, and time to market n NEEK demonstrates what Nios II processor can accomplish n Nios II performance ranges from 17 -300 DMIPS n SOPC Builder makes system integration easier © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, Hard. Copy, Nios, Quartus, and Mega. Core are trademarks of Altera Corporation 37