FPGA for Dummies Modern FPGA architecture ESS FPGA

FPGA for Dummies Modern FPGA architecture ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA for Dummies • Historical introduction, where we come from; • FPGA Architecture: Ø basic blocks (Logic, FFs, wires and IOs); Ø additional elements; • FPGA Programming: ØDesign flow; ØSoftware; • FPGA DSP: ØDigital filters examples; ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA for Dummies • Historical introduction, where we come from; • FPGA Architecture: Ø basic blocks (Logic, FFs, wires and IOs); Ø additional elements; • FPGA Programming: ØDesign flow; ØSoftware; • FPGA DSP: ØDigital filters examples; ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

Field Programmable Gate Arrays (FPGAs) FPGAs initially were Similar to CPLDs, so a function to be implemented in FPGA is partitioned into modules (each implemented in a logic block) and then the logic blocks are connected with the programmable interconnection: ARRAY of logic GATES is the G and A in FPGA. By way of a configuration file or bit stream, an FPGA can be configured to implement the user’s desired function: this allows customization at the user’s electronics bench, or even in the final end product. This is why FPGAs are FIELD PROGRAMMABLE. ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

Basic FPGA Architecture The basic structure of an FPGA is composed of the following elements: Ø Look-up table (LUT): This element performs logic operations Ø Flip-Flop (FF): This register element stores the result of the LUT Ø Wires: These elements connect elements to one another, both Logic and clock Ø Input/Output (I/O) pads: These physically available ports get signals in and out of the FPGA. ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Architecture Contemporary FPGA architectures incorporate the basic elements along with additional computational and data storage blocks that increase the computational density and efficiency of the device. The combination of these elements provides the FPGA with the flexibility to implement any software algorithm running on a processor. ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Architecture These additional elements, which are discussed in the following sections, are: Ø Embedded memories for distributed data storage; Ø Phase-locked loops (PLLs) for driving the FPGA fabric at different clock rates; Ø High-speed serial transceivers; Ø Off-chip memory controllers; Ø Multiply-accumulate blocks; Ø Embedded processors. ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Architecture These additional elements, which are discussed in the following sections, are: Ø Embedded memories for distributed data storage; Ø Phase-locked loops (PLLs) for driving the FPGA fabric at different clock rates; Ø High-speed serial transceivers; Ø Off-chip memory controllers; Ø Multiply-accumulate blocks; Ø Embedded processors. ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: memory Using LUTs as registers does not provide enough space or versatility, so the FPGA fabric includes embedded memory elements that can be used as random-access memory (RAM), read-only memory (ROM), or shift registers. These elements are block RAMs (BRAMs), LUTs, and shift registers. Using LUTs as SRAM, this is called DISTRIBUTE RAM Included dedicated RAM components in the FPGA fabric are called BLOCKs RAM ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: memory The 7 series families have the same Block RAM/FIFO (36 Kb or 18 kb+18 kb): this components has multiple configuration options; Ø Integrated Error Correction Ø FIFO Logic ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: memory Single-Port Block RAM True Dual-Port Block RAM Simple Dual-Port Block RAM Cascading Example: Cascade 8 block RAMs to build 256 -Kb memory ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: memory Full featured FIFO: Ø Synchronous or asynchronous read and write clocks; Ø Full, empty, programmable almost-full/empty flags; Ø Optional first-word-fall-through ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: memory Altera Cyclone II embedded memory structure consist of columns of M 4 k memory blocks; ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: memory Altera Stratix II embedded memory structure consist of Tri. Matrix of M 512, M 4 k and big M-RAM memory blocks; ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Architecture These additional elements, which are discussed in the following sections, are: Ø Embedded memories for distributed data storage; Ø Phase-locked loops (PLLs) for driving the FPGA fabric at different clock rates; Ø High-speed serial transceivers; Ø Off-chip memory controllers; Ø Multiply-accumulate blocks; Ø Embedded processors. ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: clocking All synchronous designs need at least one external clock reference, many designs require several clock sources!!! Modern applications have complex clocking requirements: Ø Extremely high-performance clock signals; Ø Support for multiple frequency domains across a wide frequency range; Ø De-skewing of clocks relative to one another; Ø Low jitter and precise duty cycle to maintain the widest possible data valid window; Ø Lowest possible system power ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: clocking ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: clocking Clock regions: Ø Each clock region is 50 CLBs high and spans half the device: Ø 12 global clock networks (Driven by BUFH); Ø 4 regional clock networks (Driven by BUFR); Ø 4 I/O clock networks (Driven by BUFIO). ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: clocking Vertical Spines: Ø Global clock networks allow clocks to be distributed to potentially every clocked element on the die; Ø Global clocks are driven by BUFGCTRL located in the middle of the die; Ø Each BUFGCTRL drives a vertical spine in the center of the die that runs from the bottom to the top of the die; ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: clocking Horizontal Spines: Ø Each clock region has 12 horizontal spines for carrying global clocks: Ø Clock regions on left and right have 12 independent horizontal spines; Ø These horizontal spines can drive all clocked resources within the region; Ø Each horizontal spine is driven by a BUFH; ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: clocking Regional Clock Networks: Ø These regional networks can drive all clocked resources within the region; Ø Each horizontal spine is driven by a BUFR; ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: clocking CLB Resources: Ø In every region there are 12 horizontal spines of the global clock network and 4 regional clocks; Ø All 16 clocks can clock resources within the region; Ø Only 12 of the 16 can enter the double column of CLBs in the top and bottom half of the clock region ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: clocking There are up to 24 Clock Management Tiles (CMT) per device, each one contains: Ø One Mixed-Mode Clock Manager (MMCM), that is used to generate multiple clocks with defined phase and frequency relationships to a given input clock. Ø one PLL, primarily intended for use with the I/O phaser for high speed memory controllers or with high requirement analog clocks. ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Architecture These additional elements, which are discussed in the following sections, are: Ø Embedded memories for distributed data storage; Ø Phase-locked loops (PLLs) for driving the FPGA fabric at different clock rates; Ø High-speed serial transceivers; Ø Off-chip memory controllers; Ø Multiply-accumulate blocks; Ø Embedded processors. ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: High Speed Tranceivers To communicate between FPGAs or to other devices, it’s more convenient to use high speed differential connection instead of parallel one, to reduce noise spikes. Many standard protocol use this approach for the physical layer: Fibre Channel, Infini. Band, PCI Express, Rapid. IO, Sky. Rail , Gigabit Ethernet, etc… ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: High Speed Tranceivers Ø TX: From the FPGA fabric a parallel bus is encoded to increase the robustness against the noise and to reduce the DC component and then serialized; Ø RX: the received differential signal is used to reconstruct the clock, and then decoded and re -parallelized. ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: High Speed Tranceivers Xilinx Multi-Gigabit Transceiver have different name depending on the maximum speed that they support: Ø GTP (6, 6 Gbps); Ø GTX (12, 5 Gbps); Ø GTH (16, 3 Gbps); Ø GTY (32, 75 Gbps). ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: High Speed Tranceivers ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: High Speed Tranceivers The Arria 10 FPGA and So. C transceivers have a versatile feature set to handle a wide range of links and provide error-free link operation ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Architecture These additional elements, which are discussed in the following sections, are: Ø Embedded memories for distributed data storage; Ø Phase-locked loops (PLLs) for driving the FPGA fabric at different clock rates; Ø High-speed serial transceivers; Ø Off-chip memory controllers; Ø Multiply-accumulate blocks; Ø Embedded processors. ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: Off-chip memory controllers FPGA devices provide memory interface support, including serial and parallel interfaces. Ø Serial memory: Hybrid Memory Cube (HMC) is the latest technology; Ø Parallel Memory: latest devices offer parallel memory support up to high rate for DDR 4 and supports a wide range of other protocols like o DDR 3 / DDR 3 L, LPDDR 3; o DDR 2; o Mobile DRAMs; o QDRII+ SRAM; ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Architecture These additional elements, which are discussed in the following sections, are: Ø Embedded memories for distributed data storage; Ø Phase-locked loops (PLLs) for driving the FPGA fabric at different clock rates; Ø High-speed serial transceivers; Ø Off-chip memory controllers; Ø Multiply-accumulate blocks; Ø Embedded processors. ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: multiplier XILINX Spartan 3 (2004) include on the side of each BRAM a multiplier block (18 x 18) ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: multiplier Altera Cyclone II has one to three columns of embedded multipliers; each embedded multiplier can be configured to support : Ø One 18 x 18 multiplier Ø Two 9 x 9 multipliers ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: Xtreme. DSP Starting with Virtex 4 family, Xilinx introduced DSP 48 block for highspeed DSP on FPGAs Essentially a multiply-accumulate core with many other features ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: Xtreme. DSP Adder Out = (Z ± (X + Y + CIN)) ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: DSP unit Also Altera include in the Stratix III family a DSP Unit ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Architecture These additional elements, which are discussed in the following sections, are: Ø Embedded memories for distributed data storage; Ø Phase-locked loops (PLLs) for driving the FPGA fabric at different clock rates; Ø High-speed serial transceivers; Ø Off-chip memory controllers; Ø Multiply-accumulate blocks; Ø Embedded processors. ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: Embedded Microprocessor Cores Xilinx Virtex-II Pro include a Power. PC™ 405 Core 1. Processor Block 2. Rocket. IO Multi-Gigabit Transceivers 3. CLB and Configurable Logic 4. Select. IO-Ultra 5. Digital Clock Managers 6. Multipliers and Block Select. RAM ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: Embedded Microprocessor Cores Xilinx Zynq is an Innovative ARM® + FPGA architecture for differentiation, analytics & control. Ø Zynq-7000 So. C uses a Dualcore ARM® Cortex™-A 9 MPCore™ with Core. Sight™ up to 1 GHz; Ø Zynq Ultra. Scale+ MPSo. C uses a Quad-core ARM® Cortex™A 53 MPCore up to 1. 5 GHz with a Real-Time Processing Unit Dual-core ARM® Cortex™-R 5 MPCore up to 600 MHz ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

FPGA Components: Embedded Microprocessor Cores Also Altera has ARM® + FPGA architectures: Ø Arria 10 So. Cs, includes a dual-core ARM® Cortex™A 9 MPCore™ hard processor system (HPS); Ø Stratix 10 FPGA and So. C system includes ad-core 64 bit ARM® Cortex®-A 53 hard processor system up to 1. 5 GHz; ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

Questions ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna

ESS | FPGA for Dummies | 2015 -12 -15| Maurizio Donna