Electronics in High Energy Physics Introduction to Electronics

Electronics in High Energy Physics Introduction to Electronics in HEP Field Programmable Gate Arrays Part 1 based on the lecture of S. Haas

Outline Part 1 • Programmable Logic • CPLD • FPGA – – Architecture Examples Features Vendors and Devices coffee break Part 2 • VHDL – Introduction – Examples • Design Flow – – Entry Methods Simulation Synthesis Place & Route • IP Cores • CERN Tools & Support 2

Programmable Logic

Programmable Logic • Programmable digital integrated circuit • Standard off-the-shelf parts • Desired functionality is implemented by configuring on-chip logic blocks and interconnections • Advantages (compared to an ASIC): – Low development costs – Short development cycle – Device can (usually) be reprogrammed • Types of programmable logic: – Complex PLDs (CPLD) – Field programmable Gate Arrays (FPGA) 4

CPLD Architecture and Examples

PLD - Sum of Products Programmable AND array followed by fixed fan-in OR gates A B C Programmable switch or fuse AND plane 6

PLD - Macrocell Can implement combinational or sequential logic Select A B C Enable Flip-flop MUX D Q Clock AND plane 7

CPLD Structure PLD Block • • • I/O Block Integration of several PLD blocks with a programmable interconnect on a single chip Interconnection Matrix I/O Block • • • PLD Block 8

CPLD Example - Altera MAX 7000 EPM 7000 Series Block Diagram 9

CPLD Example - Altera MAX 7000 EPM 7000 Series Device Macrocell 10

FPGA Architecture

FPGA - Generic Structure FPGA building blocks: Interconnection switches I/O I/O • Programmable logic blocks Implement combinatorial and sequential logic • Programmable interconnect Wires to connect inputs and outputs to logic blocks • Programmable I/O blocks Special logic blocks at the periphery of device for external connections Logic block I/O 12

Other FPGA Building Blocks • Clock distribution • Embedded memory blocks • Special purpose blocks: – DSP blocks: • Hardware multipliers, adders and registers – Embedded microprocessors/microcontrollers – High-speed serial transceivers 13

FPGA – Basic Logic Element • LUT to implement combinatorial logic • Register for sequential circuits • Additional logic (not shown): – Carry logic for arithmetic functions – Expansion logic for functions requiring more than 4 inputs Select Out A B C D LUT D Q Clock 14

Look-Up Tables (LUT) • Look-up table with N-inputs can be used to implement any combinatorial function of N inputs • LUT is programmed with the truth-table A B C D LUT Z LUT implementation A B Z C D Truth-table Gate implementation 15

LUT Implementation • Example: 3 -input LUT • Based on multiplexers (pass transistors) • LUT entries stored in configuration memory cells X 1 X 2 0/1 0/1 F 0/1 0/1 Configuration memory cells 0/1 X 3 16

Programmable Interconnect • Interconnect hierarchy (not shown) – Fast local interconnect – Horizontal and vertical lines of various lengths LE LE Switch Matrix LE LE 17

Switch Matrix Operation Before Programming After Programming • 6 pass transistors per switch matrix interconnect point • Pass transistors act as programmable switches • Pass transistor gates are driven by configuration memory cells 18

Special Features • Clock management – PLL, DLL – Eliminate clock skew between external clock input and on-chip clock – Low-skew global clock distribution network • • Support for various interface standards High-speed serial I/Os Embedded processor cores DSP blocks 19

Configuration Storage Elements • Static Random Access Memory (SRAM) – each switch is a pass transistor controlled by the state of an SRAM bit – FPGA needs to be configured at power-on • Flash Erasable Programmable ROM (Flash) – each switch is a floating-gate transistor that can be turned off by injecting charge onto its gate. FPGA itself holds the program – reprogrammable, even in-circuit • Fusible Links (“Antifuse”) – Forms a forms a low resistance path when electrically programmed – one-time programmable in special programming machine – radiation tolerant 20

Example: Altera Stratix Series

Floorplan 22

Logic Element 23

Logic Array Block (LAB) • LAB regroups 10 logic elements with a fast local interconnect • Interconnect structure – Direct link between LABs and adjacent blocks – Row interconnects • 4, 8, and 24 blocks left or right – Column interconnects • 4, 8, and 16 blocks up or down 24

Embedded Memory Dual-Port RAM – M 512 – 512 x 1 – M 4 K – 4096 x 1 – M-RAM – 64 K x 8 25

Example: Xilinx Virtex-II Pro

Virtex II Pro Floorplan Up to 16 serial transceivers • 622 Mbps to 3. 125 Gbps Power. PCs • 1 to 4 Power. PCs • 4 to 16 multi-gigabit transceivers • 12 to 216 multipliers • 3, 000 to 50, 000 logic cells • 200 k to 4 M bits RAM • 204 to 852 I/Os Logic cells 27

Logic Slice Architecture • Two 4 -input LUT, can also be used as: – 16 -bit synchronous RAM – 16 -bit shift register • Two flip-flops/latches • Carry logic for arithmetic circuits (e. g. adder) • Fast width expansion logic – Implement logic functions with more than 4 inputs 28

Configurable Logic Block (CLB) • CLB regroups 4 logic slices • Fast connection to neighbors • Connections for carry logic and shift register mode 29

Xilinx: Embedded Multipliers 30

Altera: Embedded DSP Blocks • Two DSP Block columns per device • Number varies by height of column • Can implement: – Eight 9 x 9 multipliers – Four 18 x 18 multipliers – One 36 x 36 multiplier • Contains adder/subtractor/accumulator • Registered inputs can become shift register 31

Altera: Embedded DSP Block 32

Xilinx: Rocket I/O 3. 125 Gb/s per pair 32 b @ 78 MHz Virtex-II Pro Virtex 4: 11. 1 Gbps !!! 33

FPGA Vendors & Device Families • Xilinx – Virtex-II/Virtex-4: Featurepacked high-performance SRAM-based FPGA – Spartan 3: low-cost feature reduced version – Cool. Runner: CPLDs • Altera – Stratix/Stratix-II • High-performance SRAMbased FPGAs • Actel – Anti-fuse based FPGAs • Radiation tolerant – Flash-based FPGAs • Lattice – Flash-based FPGAs – CPLDs (EEPROM) • Quick. Logic – Via. Link-based FPGAs – Cyclone/Cyclone-II • Low-cost feature reduced version for cost-critical applications – MAX 3000/7000 CPLDs – MAX-II: Flash-based FPGA 34

State of the Art in FPGAs • 90 nm process on 300 mm wafers – Lower cost per function (LUT + register) – Smaller and faster transistors: Higher speed • System speed up to 500 MHz – Mainly through smart interconnects, clock management, dedicated circuits, flexible I/O. – Integrated transceivers running at 10 Gigabits/sec • More Logic and Better Features: – >100, 000 LUTs & flip-flops – >200 embedded RAMs, and same number 18 x 18 multipliers • 1156 pins (balls) with >800 GP I/O – 50 I/O standards, incl. LVDS with internal termination • 16 low-skew global clock lines – Multiple clock management circuits • On-chip microprocessor(s) and multi-Gbps transceivers 35

Latest Devices: Capacity & Features Xilinx Virtex-4 Altera Stratix-II • • 90 nm process Up to 960 I/Os >200000 logic cells Up to 552 18 kb block RAMs (~10 Mb RAM) • 192 DSP slices (18 x 18 multiplier-accumulator) • 20 digital clock managers (DCM) • • • 24 high-speed serial transceivers (622 Mb/s to 11. 1 Gb/s) • Up to four Power. PC 405 cores • Serial I/O up to 1 Gb/s 90 nm process Up to 1170 I/Os 179000 logic elements 9. 6 Mb embedded RAM 96 DSP blocks: 380 18 x 18 multipliers • 12 PLLs • No hard processor cores 36