Introduction to Sequential Design Types of Logic Circuits

Introduction to Sequential Design

Types of Logic Circuits ¡ Logic circuits can be: l Combinational Logic Circuits-outputs depend only on current inputs l Sequential Logic Circuits-outputs depends not only on current inputs but also on the past sequence of inputs

Sequential Circuit Models

Combinational Logic Delay Longest delay Shortest delay Longest timing delay = 5 ns+5 ns+5 ns = 20 ns Shortest timing delay = 5 ns We will use the longest delay to represent the combinational logic (CL) delay, tcl

Combinational Logic (CL) Cloud Model Tcl=20 ns

Memory

Memory ¡ We will add memory (or registers) to our logic circuits. This will allow us to design sequential circuits.

Registers ¡ We will represent registers with the following block diagram Clock and reset are control signals Ns and ps are data signals

Sequential Systems Block Diagrams

Sequential Systems General Block Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset CL= Combinational Logic Cloud Reg= D Registers

Sequential Systems General Block Diagram Next State Present State Output Vector Input Vector Clock Reset Feedback Path X is the input data vector Y is the output data vector

Sequential Systems Block Diagram Next State Present State Output Vector Input Vector Clock Reset Feedback Path Ns is the next state data vector Ps is the present state data vector

Sequential Systems Block Diagram Next State Present State Output Vector Input Vector Clock Reset Feedback Path Notice we have a feedback path which combines the ps data vector with the input vector to generate a new ns data vector.

Sequential Systems Block Diagram Next State Present State Output Vector Input Vector Clock Reset Mathematically, we say Feedback Path Or, ns is a function F of X and ps and Y is a function H of ps.

F Logic Example Register Circuit Schematic X input ns ps H Logic (buffer) Block Diagram

F Logic Example Register Circuit Schematic X input ns State Equations ps H Logic (buffer)

Finite State Machine (FSM) General Models

Moore FSM General Block Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset CL= Combinational Logic Cloud Reg= D Registers

Moore FSM State Equations Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

Mealy FSM Block Diagram and State Equations Next State Present State Input Vector Output Vector Feedback Path Output Y is also a function of input X

Mealy-Moore FSM Block Diagram and State Equations Next State Present State Input Vector Mealy Outputs Moore Outputs

State Diagrams

State Bubble

State Bubble Example Conditional Transition Unconditional Transition State name = S 0 State value = 00 Y = 0 for this state We leave this state if upn=1, We remain in this state if upn=0

Memory Devices

Memory Devices Data Latch (D-latch) ¡ Flip-flops (edge triggered) ¡ l l l D-FF, D Register JK-FF T-FF

D-FF Positive Edge Triggered Block Diagram Symbol 4 inputs: D, Clk, Pre, Rst One output: Q D = Data Input Clk = Clock Input Pre = Preset Input Rst = Reset Input

D-FF Truth Table Symbol Truth Table Equation (rising clock) D Clk d d 1 0 0 d d 0 1 1 d 1 1 1 0 1 1

D-FF Truth Table Symbol Truth Table Equation (rising clock) D Clk d d 1 0 0 d d 0 1 1 d 1 1 1 0 1 1 Pre= Preset Input (active low) Rst = Reset Input (active low) Highest priority

D-FF Truth Table Symbol Truth Table Equation (rising clock) D Clk d d 1 0 0 d d 0 1 1 d 1 1 1 0 1 1 D = Data Input Clk = Clock input Qn = Register Output

FSM Examples

Example– 2 -bit Up Counter ¡ State Diagram Clock is implied

Example – 2 -bit Up Counter ¡ State Table ps S 0 S 1 S 2 S 3 ns S 1 S 2 S 3 S 0 State Value Assignment y 0 1 2 3 Let S 0 = reset state Let S 0 = 00 S 1 = 01 S 2 = 10 S 3 = 11 Output Vector

Example – 2 -bit Up Counter ¡ Truth Table ps 1 ps 0 ns 1 ns 0 0 1 0 1 0 1 1 0 0 y 1 0 0 1 1 y 0 0 1

Example – 2 -bit Up Counter ¡ Excitation Equations

Moore FSM Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

Logic Diagram Reg Block F Logic Y Vector H Logic No X Vector in this Example No H Logic needed

Logic Diagram

Flash Animation

Example 3– 2 -bit Down Counter ¡ State Diagram Clock is implied

Example – 2 -bit Down Counter ¡ State Table ps S 0 S 3 S 2 S 1 ns S 3 S 2 S 1 S 0 y 0 3 2 1 Let S 0 = reset state Let S 0 = 00 S 1 = 01 S 2 = 10 S 3 = 11

Example – 2 -bit Down Counter ¡ Truth Table ps 1 ps 0 ns 1 ns 0 0 0 1 1 0 0 1 1 0 y 1 0 0 1 1 y 0 0 1

Example – 2 -bit Down Counter ¡ Excitation Equations

Recall Moore FSM Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

Logic Diagram Reg Block F Logic Y Vector H Logic No X Vector in this Example

Logic Diagram

Example 4 – 2 -bit Up/Down Counter ¡ State Diagram

Example – 2 -bit Up/Down Counter ¡ State Diagram Shorthand Notation

Example – 2 -bit Up/Down Counter ¡ State Table ps S 0 S 1 S 2 S 3 ns ns upn S 1 S 2 S 3 S 0 S 1 S 2 Let S 0 = reset state y Let 0 1 2 3 S 0 = 00 S 1 = 01 S 2 = 10 S 3 = 11

¡ Example – 2 -bit Up/Down Counter Truth Table upn ps 1 ps 0 0 0 1 1 ns 1 0 1 1 0 ns 0 1 0 y 1 0 0 1 1 y 0 0 1 1 0 0 1 0 1 0 0 0 1 1 1 1 0 1 1

Example – 2 -bit Up/Down Counter ¡ Excitation Equations

Recall Moore FSM Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

Logic Diagram Reg Block X Vector F Logic Y Vector H Logic

Logic Diagram

Example 5– 3 -bit Arbitrary Counter Design a 3 -bit arbitrary counter that will count in the following sequence 3, 2, 3, 1, 2, 3 If a state is not used reset it to state zero. ¡ • • • How may states do we have? How many registers do we need? How many bits do we need for Y?

Example 5– 3 -bit Arbitrary Counter ¡ State Diagram

Example – Arbitrary 3 -bit Counter ¡ State Table Assign State Values ps S 0 S 1 S 2 S 3 ns S 1 S 2 S 3 S 4 y 3 2 3 1 S 4 S 0 2 S 5 S 0 0 S 6 S 0 0 S 7 S 0 0 Let S 0 = 000 S 1 = 001 S 2 = 010 S 3 S 4 S 5 S 6 S 7 = = = 011 100 101 110 111 Let S 0 = reset state

Develop Truth Table

Example – 2 -bit Arbitrary Counter ¡ Develop Excitation Equations -- F Logic

Develop Excitation Equations for Y Y 1 Y 0

Example – 2 -bit Arbitrary Counter ¡ Excitation Equations -- H Logic

Recall Moore FSM Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

Logic Circuit R E G F H

Logic Circuit

Simulation

Example 5– 2 -bit Up/Down Counter with Active Low Enable and Synchronous RESET (SRESET) ¡ State Diagram Clock is implied

Example – 2 -bit Up/Down Counter with Enable and SRESET ¡ Functional Table srn en upn Function 0 d d 1 1 d Hold 1 0 0 Count Up 1 0 1 Count Down Highest Level of Priority Synchronous Reset (sreset) Lowest Level of Priority

State Table Srn En 0 1 1 1 d 1 0 0 up n d d 0 1 ns S 0 ps ps+1 ps -1

Truth Table (5 variables!!) Although, we could design this circuit directly from the truth table we will use design partitioning.

Moore FSM Architecture Next State Present State Output Vector Input Vector Feedback Path

Partitioned Design srn en We have Srn En ns 0 d S 0 1 1 PS 1 0 Count Note, with the partitioned design we can “reuse” already designed submodules to create the “new” design.

Top Level Block Diagram

UP/Down Logic Circuit Symbol

Register Block Symbol Logic Circuit

2 Bit 4 x 1 Mux Circuit Symbol

1 -bit 4 x 1 Mux Logic Circuit Symbol

1 -bit 2 x 1 Mux Logic Circuit Symbol

Top Level Block Diagram

Simulation

Example 6 – FSM Controller State Diagram

Truth Table for NS Truth Table

Kmaps for NS 1 and NS 0 NS 1 NS 0

Truth Table and Equations for Y Truth Table Recall, Moore FSM, so Y will Not be a function of T By Inspection

Logic Circuit F R E G H

Simulation

Memory Devices

Flip-Flops

D-FF Truth Table Qn follows D on Rising Edge of CLK Symbol Truth Table Equation (rising clock) D Clk d d 1 0 0 d d 0 1 1 d 1 1 1 0 1 1 D = Data Input Clk = Clock input Qn = Register Output

T-FF (Toggle) Changes state on every tick of CLK Symbol Equation (rising clock) T Clk D d 1 0 0 D d 0 1 1 d 1 1 1 0 1 1 1 Truth Table

SR-FF Set =>Qn=1 Reset=>Qn=0 Symbol Equation (rising clock) S R Clk d d d 1 0 0 d d d 0 1 1 d d 1 1 1 0 0 1 1 1 1 ? ? ? Truth Table

JK-FF Symbol Equation (rising clock) J K Clk d d d 1 0 0 d d d 0 1 1 d d 1 1 1 0 0 1 1 1 1 Truth Table

Example: Design a JK-FF using only Logic and a D-FF Symbol J K Clk d d d 1 0 0 d d d 0 1 1 d d 1 1 1 0 0 1 1 1 1 Truth Table

Example State Diagram Let s 0=0 and s 1=1 State Table

JK-FF Truth Table Logic Equations

Recall Moore FSM State Equations Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

F Logic JK Example D-Register Circuit Schematic X input ns ps H Logic (buffer) Block Diagram

JK Example Circuit Schematic Simulation

Latches

D-Latch Block Diagram Symbol 4 inputs: D, E, Pre, Rst One output: Q D = Data Input E = Enable Input Pre = Preset Input Rst = Reset Input

D-Latch Truth Table Symbol Truth Table D E d d 1 0 0 d d 0 1 1 1 1 1

D-Latch State Equations Symbol Equation Truth Table (level clock) D E d d 1 0 0 d d 0 1 1 1 1 1

SR-Latch State Equations Symbol Equation Truth Table (level clock) S R d d 1 0 0 d d 0 1 1 1 0 1 1 1 1 ? ? ?

Example T-FF D-Latch

Simulation

Modular Sequential Logic

Shift Registers Logic Design which manipulates the bit position of binary data by shifting it to the left or right. ¡ Major application ¡ l Serial Data to Parallel Data converters

Example ¡ Design a three-bit shift register with the following functions S 1 S 0 Function 0 0 0 1 Shift Right 1 0 Shift Left 1 1 No Shift Synchronous Reset (sreset)

Partitioned Design

No Shift Equations and Circuit

Shift Left Equations and Circuit

Shift Right Equations and Circuit

Synchronous Reset Module

Registers

Total Design