FINITE STATE MACHINES II n STATE MINIMIZATION n

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FINITE STATE MACHINES - II n STATE MINIMIZATION n n n ANALYSIS OF SYNCHRONOUS

FINITE STATE MACHINES - II n STATE MINIMIZATION n n n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS n n PARTITIONING MINIMIZATION PROCEDURE VENDING MACHINE EXAMPLE PROCEDURE EXAMPLE ALGORITHMIC STATE MACHINES (ASM) CHARTS COMPLETE FSM DESIGN EXAMPLE PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR _________________________ n ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 1

FINITE STATE MACHINES - II n STATE MINIMIZATION n PARTITIONING MINIMIZATION PROCEDURE n n

FINITE STATE MACHINES - II n STATE MINIMIZATION n PARTITIONING MINIMIZATION PROCEDURE n n n DEFINITION: Two states Si and Sj are said to be equivalent if and only if for every input sequence , the same output sequence will be produced regardless of whether Si or Sj are the initial states. DEFINITION OF 1 -SUCCESSOR : If the machine moves from state Si to state Sv when input w = 1, then we say that Sv is a 1 -successor of Si DEFINITION OF 0 -SUCCESSOR : If the machine moves from state Sj to state Su when input w = 0, then we say that Su is a 0 -successor of Si IF STATES Si AND Sj ARE EQUIVALENT, THEN THEIR CORRESPONDING K-SUCCESSORS (FOR ALL K) ARE ALSO EQUIVALENT. _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 2

FINITE STATE MACHINES - II n STATE MINIMIZATION n PARTITIONING MINIMIZATION PROCEDURE (CONTINUES) n

FINITE STATE MACHINES - II n STATE MINIMIZATION n PARTITIONING MINIMIZATION PROCEDURE (CONTINUES) n DEFINITION: A PARTITION CONSISTS OF ONE OR MORE BLOCKS, WHERE EACH BLOCK COMPRISES A SUBSET OF STATES THAT MAY BE EQUIVALENT, BUT THE STATES IN A GIVEN BLOCK ARE DEFINITELY NOT EQUVALENT TO THE STATES IN THE OTHER BLOCK. _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 3

FINITE STATE MACHINES - II n STATE MINIMIZATION n PARTITIONING MINIMIZATION PROCEDURE (CONTINUES) n

FINITE STATE MACHINES - II n STATE MINIMIZATION n PARTITIONING MINIMIZATION PROCEDURE (CONTINUES) n PROCEDURE: n n 1) ALL STATES BELONG TO THE INITIAL PARTITION P 1 2) P 1 IS PARTITIONED IN BLOCKS SUCH THAT THE STATES IN EACH BLOCK GENERATE THE SAME OUTPUT. 3) CONTINUE TO PERFORM NEW PARTITIONS BY TESTING WHETHER THE K-SUCCESSORS OF THE STATES IN EACH BLOCK ARE CONTAINED IN ONE BLOCK. THOSE STATES WHOSE K-SUCCESSORS ARE IN DIFFERENT BLOCKS CANNOT BE IN ONE BLOCK. 4) PRCEDURE ENDS WHEN A NEW PARTITION IS THE SAME AS. THE PREVIOUS PARTITION 4

FINITE STATE MACHINES - II n STATE MINIMIZATION n PARTITIONING MINIMIZATION PROCEDURE (CONTINUES) n

FINITE STATE MACHINES - II n STATE MINIMIZATION n PARTITIONING MINIMIZATION PROCEDURE (CONTINUES) n EXAMPLE: Consider the following state transition table Next state Present state w= 0 w= 1 Output z A B C D E F G B D F B F E F C F E G C D G 1 1 0 0 0 P 1 = (ABCDEFG) P 2 = (ABD)(CEFG) Diff. Outputs. Because (CEFG) 0 -successors are (FFEF) in same block, (CEFG) 1 -successors are (ECDG) in diff. block, F must be different from C, E and G P 3 = (ABD)(CEG)(F) P 4 = (AD)(B)(CEG)(F) Same process for (AD) and (CEG) gives P 5 = (AD)(B)(CEG)(F) P 5 = P 4 5

FINITE STATE MACHINES - II n STATE MINIMIZATION n PARTITIONING MINIMIZATION PROCEDURE (CONTINUES) EXAMPLE

FINITE STATE MACHINES - II n STATE MINIMIZATION n PARTITIONING MINIMIZATION PROCEDURE (CONTINUES) EXAMPLE (CONTINUES): MINIMAL STATE TRAMSITION TABLE ORIGINAL TABLE n Present state A B C D E F G Next state w= 0 w= 1 Output z B D F B F E F C F E G C D G 1 1 0 0 0 P 4 = (AD)(B)(CEG)(F) MINIMIZED TABLE Nextstate Present state w= 0 w= 1 Output z A B C F B A F C C F C A 1 1 0 0 6

FINITE STATE MACHINES - II n STATE MINIMIZATION n VENDING MACHINE EXAMPLE Design an

FINITE STATE MACHINES - II n STATE MINIMIZATION n VENDING MACHINE EXAMPLE Design an FSM that will dispense candy under the following conditions: n n n 1. 2. 3. - The machine accepts nickels and dimes 15 cents releases a candy from the machine If 20 cents is deposited, the machine will not return the change, but it credit the buyer with 5 cents and wait for the buyer to make a second purchase _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 7

FINITE STATE MACHINES - II n STATE MINIMIZATION n VENDING MACHINE EXAMPLE (Continues) Clock

FINITE STATE MACHINES - II n STATE MINIMIZATION n VENDING MACHINE EXAMPLE (Continues) Clock sense N sense D N D (a) Timing diagram _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 8

FINITE STATE MACHINES - II n STATE MINIMIZATION n VENDING MACHINE EXAMPLE (Continues) N

FINITE STATE MACHINES - II n STATE MINIMIZATION n VENDING MACHINE EXAMPLE (Continues) N sense N Clock D Q Q (b) Circuit that generates N _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 9

FINITE STATE MACHINES - II STATE MINIMIZATION: VENDING MACHINE EXAMPLE (Continues) DN Reset DN

FINITE STATE MACHINES - II STATE MINIMIZATION: VENDING MACHINE EXAMPLE (Continues) DN Reset DN S 1¤ 0 DN DN DN S 4¤ 1 N DN D N S 2¤ 0 S 3¤ 0 D N DN S 6¤ 0 S 5¤ 1 N D S 7¤ 1 DN DN D S 8¤ 1 S 9¤ 1 _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 10

FINITE STATE MACHINES - II n STATE MINIMIZATION n VENDING MACHINE EXAMPLE (Continues) Next

FINITE STATE MACHINES - II n STATE MINIMIZATION n VENDING MACHINE EXAMPLE (Continues) Next state Present Output state DN =00 01 10 11 z P 1 = (S 1, S 2, S 3, S 4, S 5, S 6, S 7, S 8, S 9) P 2 = (S 1, S 2, S 3, S 6)(S 4, S 5, S 7, S 8, S 9) P 3 = (S 1)(S 3)(S 2, S 6)(S 4, S 5, S 7, S 8, S 9) P 4 = (S 1)(S 3)(S 2, S 6)(S 4, S 7, S 8)(S 5, S 9) P 5 = (S 1)(S 3)(S 2, S 6)(S 4, S 7, S 8)(S 5, S 9) S 1 S 3 S 2 – 0 S 2 S 4 S 5 – 0 S 3 S 6 S 7 – 0 S 4 S 1 – – – 1 S 5 S 3 – – – 1 S 6 S 8 S 9 – 0 S 7 S 1 – – – 1 S 8 S 1 – – – 1 S 9 S 3 – – – 1 _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 11

FINITE STATE MACHINES - II STATE MINIMIZATION: VENDING MACHINE EXAMPLE (Continues) DN MINIMIZED STATE

FINITE STATE MACHINES - II STATE MINIMIZATION: VENDING MACHINE EXAMPLE (Continues) DN MINIMIZED STATE TRANSITION TABLE AND DIAGRAM S 1¤ 0 Next state Present Output state DN =00 01 10 11 z S 1 S 2 S 3 S 4 S 5 S 1 S 2 S 3 S 1 S 3 S 2 S 4 S 5 S 2 S 4 – – – – – 0 0 0 1 1 N DN D DN S 3¤ 0 DN N DN S 2¤ 0 D S 5¤ 1 N D S 4¤ 1 12

FINITE STATE MACHINES - II STATE MINIMIZATION: VENDING MACHINE EXAMPLE (Continues) MINIMIZED STATE TRANSITION

FINITE STATE MACHINES - II STATE MINIMIZATION: VENDING MACHINE EXAMPLE (Continues) MINIMIZED STATE TRANSITION DIAGRAM: Moore-type versus Mealy-type DN¤ 0 DN MOORE-TYPE MEALY_TYPE S 1¤ 0 DN D DN N¤ 0 N DN¤ 0 S 3¤ 0 N¤ 1 DN N DN S 2¤ 0 D¤ 1 D S 5¤ 1 D¤ 0 S 3 N¤ 0 D¤ 1 S 2 N D S 4¤ 1 DN¤ 0 13

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS n PROCEDURE: is

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS n PROCEDURE: is the reverse of the synthesis process. n n n 1. - OUTPUTS OF FLIP-FLOPS ARE THE INTERNAL STATES. 2. - INPUT EQUATIONS TO FLIP-FLOPS DETERMINE NEXT INTERNAL STATE. 3. - EXCITATION TABLE IS CONSTRUCTED FROM THESE INPUT EQUATIONS TO FLIP-FLOPS. OUTPUT EQUATIONS ARE PRODUCED. 4. - THE STATE-ASSIGNED TABLE IS PRODUCED FROM THE EXCITATION TABLE 5. - THE STATE-TRANSITION TABLE IS PRODUCED BY ASSIGNING A STATE IDENTIFICATION LETTER TO EACH ASSIGNED STATE. 6. - THE STATE-TRANSITION DIAGRAM IS PRODUCED FROM THE STATETRANSITION TABLE. _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 14

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS n EXAMPLE: ANALYZE

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS n EXAMPLE: ANALYZE THE FOLLOWING CIRCUIT Exitation equations: DY 1 = w !y 1 + w y 2 DY 2 = w y 1 + w y 2 z = y 1 y 2 Next state equations: Y 1 = DY 1 = w !y 1 + w y 2 Y 2 = DY 2 = w y 1 + w y 2 _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 15

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS EXAMPLE (Continues) Exitation

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS EXAMPLE (Continues) Exitation equations: DY 1 = w !y 1 + wy 2 DY 2= w y 1 + w y 2 z = y 1 y 2 Next state equations: Y 1 = DY 1 = w !y 1 + w y 2 Y 2 = DY 2 = w y 1 + w y 2 Present state y 2 y 1 00 01 10 11 Next State w= 0 w= 1 Y 2 Y 1 00 00 01 10 11 11 Output z 0 0 0 1 (a) State-assigned table _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 16

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS EXAMPLE (Continues) Present

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS EXAMPLE (Continues) Present state y 2 y 1 00 01 10 11 Next State w= 0 w= 1 Y 2 Y 1 00 00 01 10 11 11 Output z 0 0 0 1 Next state Present state Output w= 0 w= 1 z A B C D A A B C D D 0 0 0 1 (b) State table (a) State-assigned table _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 17

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS ANOTHER EXAMPLE: Analyze

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS ANOTHER EXAMPLE: Analyze the following circuit J 1 w K 1 J 2 J Q K Q y 1 z y 2 Clock K 2 Resetn _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 18

FINITE STATE MACHINES - II n w ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS ANOTHER EXAMPLE

FINITE STATE MACHINES - II n w ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS ANOTHER EXAMPLE (Continues) y 1 J 1 Excitation Equations J Q z J 1 = w K Q K 1 = !w + !y 2 J 2 = w y 1 K 2 = !w J 2 J Q Clock K 2 y 2 z = y 1 y 2 K Q Resetn _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 19

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS ANOTHER EXAMPLE (Continues)

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS ANOTHER EXAMPLE (Continues) Excitation Equations J 1 = w Flip-flop inputs K 1 = !w + !y 2 Present J 2 = w y 1 state w= 0 w= 1 K 2 = !w y 2 y 1 J 2 K 2 J 1 K 1 z = y 1 y 2 Output z 00 01 01 00 11 0 01 01 01 10 11 0 10 01 01 00 10 0 11 01 01 10 10 1 _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 20

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS ANOTHER EXAMPLE (Continues)

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS ANOTHER EXAMPLE (Continues) EXCITATION TABLE STATE-ASSIGNED TABLE Present state y 2 y 1 Flip-flop inputs w= 0 J 2 K 2 J 1 K 1 w= 1 J 2 K 2 J 1 K 1 Output z Present state y 2 y 1 Next State w= 0 w= 1 Y 2 Y 1 Output z 00 01 01 00 11 0 00 00 01 01 01 10 11 0 01 00 10 00 11 0 10 01 01 00 10 0 11 00 11 1 11 01 01 10 10 1 _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 21

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS EXAMPLE (Continues) Present

FINITE STATE MACHINES - II n ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS EXAMPLE (Continues) Present state y 2 y 1 00 01 10 11 Next State w= 0 w= 1 Y 2 Y 1 00 00 01 10 11 11 Output z 0 0 0 1 Next state Present state Output w= 0 w= 1 z A B C D A A B C D D 0 0 0 1 (b) State table (a) State-assigned table _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 22

FINITE STATE MACHINES - II n ALGORITHMIC STATE MACHINES (ASM) CHARTS n DEFINITION: An

FINITE STATE MACHINES - II n ALGORITHMIC STATE MACHINES (ASM) CHARTS n DEFINITION: An ASM is a type of flowchart that can be used to represent the state transitions and generated outputs for LARGE FSMs. n THREE TYPES OF ELEMENTS: n STATE BOX, DECISION BOX, CONDITIONAL OUTPUT BOX. State name Output signals or actions (Moore type) (a) State box 0 (False) Condition expression (b) Decision box 1 (True) Conditional outputs or actions (Mealy type) (c) Conditional output box _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 23

FINITE STATE MACHINES - II n n ALGORITHMIC STATE MACHINES (ASM) CHARTS (Continues) Reset

FINITE STATE MACHINES - II n n ALGORITHMIC STATE MACHINES (ASM) CHARTS (Continues) Reset Example: Moore-type Reset A w=0 A¤z=0 w=1 B¤ z = 0 w=0 0 C¤ z = 1 1 B w=1 w=0 w 0 w=1 w 1 C z 0 1 w _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 24

FINITE STATE MACHINES - II n ALGORITHMIC STATE MACHINES (ASM) CHARTS (Continues) n EXAMPLE

FINITE STATE MACHINES - II n ALGORITHMIC STATE MACHINES (ASM) CHARTS (Continues) n EXAMPLE (Mealy-type) Reset w = 1¤ z = 0 w = 0¤ z = 0 B A w = 1¤ z = 1 w = 0¤ z = 0 _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 25

FINITE STATE MACHINES - II ALGORITHMIC STATE MACHINES (ASM) CHARTS (Continues) ANOTHER EXAMPLE (ARBITER

FINITE STATE MACHINES - II ALGORITHMIC STATE MACHINES (ASM) CHARTS (Continues) ANOTHER EXAMPLE (ARBITER MOORE-TYPE FSM): FSM THAT CONTROLS THE ACCESS BY VARIOUS DEVICES TO A SHARED RESOURCE IN A GIVEN SYSTEM. ONLY ONE DEVICE CAN USE THE RESOURCE AT A TIME. Reset r 1 r 2 r 3 Reset Idle r 1 1 gnt 1 0 1 g 1 r 2 1 gnt 2 g 2 r 3 gnt 1 ¤ g 1 = 1 0 r 2 1 0 0 r 1 r 2 1 g 3 r 1 r 1 r 2 gnt 2 ¤ g 2 = 1 0 1 gnt 3 r 1 r 3 r 2 r 1 r 2 r 3 gnt 3 ¤ g 3 = 1 0 r 3 26

FINITE STATE MACHINES - II n COMPLETE FSM DESIGN EXAMPLE PARALLEL-TO-SERIAL CONVERTER WITH PARITY

FINITE STATE MACHINES - II n COMPLETE FSM DESIGN EXAMPLE PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR n Word description n Design a digital systems that will convert an 8 -bit parallel message, (b 7 , b 6 , b 5 , b 4 , b 3 , b 2 , b 1 , b 0), composed of 7 -bit ASCII character plus an initially set to 0 parity bit, into an 8 -bit serial message with the correct parity bit set into bit b 7. _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 27

FINITE STATE MACHINES - II n COMPLETE FSM DESIGN EXAMPLE PARALLEL-TO-SERIAL CONVERTER WITH PARITY

FINITE STATE MACHINES - II n COMPLETE FSM DESIGN EXAMPLE PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR n BLOCK DIAGRAM (Data Path and Control Unit) _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 28

FINITE STATE MACHINES - II n COMPLETE FSM DESIGN EXAMPLE PARALLEL-TO-SERIAL CONVERTER WITH PARITY

FINITE STATE MACHINES - II n COMPLETE FSM DESIGN EXAMPLE PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR n STATE TRANSITION TABLE _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 29

FINITE STATE MACHINES - II n COMPLETE FSM DESIGN EXAMPLE PARALLEL-TO-SERIAL CONVERTER WITH PARITY

FINITE STATE MACHINES - II n COMPLETE FSM DESIGN EXAMPLE PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR n STATE-ASSIGNED TABLE n CHOICE OF FLIP-FLOPS AND EXCITATION EQUATION Dy = Y = w y _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 30

FINITE STATE MACHINES - II n COMPLETE FSM DESIGN EXAMPLE PARALLEL-TO-SERIAL CONVERTER WITH PARITY

FINITE STATE MACHINES - II n COMPLETE FSM DESIGN EXAMPLE PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR n CIRCUIT _________________________ ECSE-323/Department of Electrical and Computer Engineering/Mc. Gill University/ Prof. Marin. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, Mc. Graw Hill. 31