Sequential Logic Adapted from Rabaeys Digital Integrated Circuits

Project Presentations What to include in presentation? • Reason for choosing the design • Final/Intended application • Design constraints • What it does/How it works • Simulations!, Simulations!!! • Layout • Post-layout simulations! • Achieved goal? Unexpected glitches? Future work • Contrast proposed schedule with actual schedule EE 415 VLSI Design

Sequential Logic Inputs Outputs COMBINATIONAL LOGIC Current State Registers Q D CLK 2 storage mechanisms • positive feedback • charge-based EE 415 VLSI Design Next state

Meta-Stability Gain should be larger than 1 in the transition region EE 415 VLSI Design

Mux-Based Latches Negative latch (transparent when CLK= 0) 1 D 0 CLK EE 415 VLSI Design Positive latch (transparent when CLK= 1) 0 Q D 1 CLK Q

Mux-Based Latch D NMOS only EE 415 VLSI Design Non-overlapping clocks

Mux-Based Latch EE 415 VLSI Design

Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states CLK D D CLK Converting into a MUX EE 415 VLSI Design Forcing the state (can implement as NMOS-only)

Reduced Clock Load Master-Slave Register EE 415 VLSI Design

Avoid Clock Overlap X CLK Q D A B CLK (a) Schematic diagram CLK EE 415 VLSI Design (b) Overlapping clock pairs

Storage Mechanisms Dynamic (charge-based) Static CLK D Q CLK Very fast Was popular, now too risky EE 415 VLSI Design

Making a Dynamic Latch Pseudo-Static Weak inverter EE 415 VLSI Design

SR-Flip Flop S Q R Q S R Q Q 0 1 0 0 1 1 Q 1 0 0 Q 0 1 0 S R Q Q 1 0 1 1 0 0 Q 1 0 1 Q 0 1 1 Q R Forbidden State S R Q Q S Q R Q Forbidden State EE 415 VLSI Design

Cross-Coupled NOR Added clock Cross-coupled NORs S R Q Q • Transistors M 5 -M 8 are wider to switch the state This is not used in datapaths any more, but is a basic building memory cell EE 415 VLSI Design

Sizing Issues Output voltage dependence on transistor width EE 415 VLSI Design Transient response For various W/L 5 and 6

Naming Conventions l In our text: » a latch is level sensitive » a register is edge-triggered l There are many different naming conventions » For instance, many books call edgetriggered elements flip-flops » This leads to confusion however EE 415 VLSI Design

Latch versus Register q Latch stores data when clock is low l Register stores data when clock rises D Q Clk Clk D D Q Q EE 415 VLSI Design Falls with data Falls with clock

Latch-Based Design • N latch is transparent when f = 0 • P latch is transparent when f = 1 f N Latch Logic EE 415 VLSI Design P Latch

Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair EE 415 VLSI Design

Master-Slave Register Multiplexer-based latch pair EE 415 VLSI Design

Timing Definitions Set-up and hold times are needed to produce a stable output CLK t tsu D D thold DATA STABLE t tc 2 Q Register q DATA STABLE t Propagation delay time affects the clock period EE 415 VLSI Design Q CLK

Characterizing Timing t. D 2 D Q Clk t. C 2 Register EE 415 VLSI Design D Q Q Clk Q t. C 2 Q Latch

Maximum Clock Frequency Minimum clock period decides - the maximum operating frequency of a sequential circuit Also: tcdreg + tcdlogic > thold tcd: contamination delay = minimum delay tclk-Q + tp, comb + tsetup = T EE 415 VLSI Design

Clk-Q Delay D Q Clk EE 415 VLSI Design

Timing of Master-Slave Register In the multiplexer-based latch pair assume that propagation delays of inverters and transmission gates are tpd_inv and tpd_tx I 2 D I 1 T 2 T 1 I 3 QM I 5 T 4 I 4 T 3 CLK The setup time states how long before the rising edge of CLK data D must be stable. D has to propagate through I 1, T 1, I 3, and I 4 before the rising edge of CLK, so tsetup=3 tpd_inv+tpd_tx The propagation delay is the time to propagate signal from QM to Q. Since the output I 4 is valid before the rising edge of the clock, so tc-q=tpd_tx+tpd_inv The hold time (time for the input to be stable after rising edge of the clock) is 0 since D and clock are delayed by the same amount before reaching the T 1 gate, so a change of D after rising edge of the clock will reach T 1 after it is shut down and will not affect its output. EE 415 VLSI Design I 6 Q

Setup Time = EE 415 VLSI Design = Output failure

More Precise Setup Time Setup and hold times defined when delay increases by 5% delay EE 415 VLSI Design

Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) EE 415 VLSI Design

Setup/Hold Time Illustrations Hold-1 case 0 EE 415 VLSI Design

Other Latches/Registers: C 2 MOS “Keepers” can be added to make circuit pseudo-static EE 415 VLSI Design

Insensitive to Clock-Overlap 0 VDD VDD M 2 M 6 M 4 D 0 X M 8 Q X D 1 M 1 (a) (0 -0) overlap EE 415 VLSI Design M 5 M 3 Q 1 M 1 (b) (1 -1) overlap M 7 M 5

Other Latches/Registers: TSPC Positive latch (transparent when CLK= 1) Negative latch (transparent when CLK= 0) Only single phase clocks are used. When f is high the latch is in the evaluate mode. When f is low the latch is in hold-mode. EE 415 VLSI Design

Including Logic in TSPC Example: logic inside the latch EE 415 VLSI Design AND latch

TSPC Register EE 415 VLSI Design

Master-Slave Flip-flops EE 415 VLSI Design

Pulse-Triggered Latches An Alternative Approach Ways to design an edge-triggered sequential cell: Master-Slave Latches Data Pulse-Triggered Latch L 1 L 2 D Q Clk Data Clk L D Q Clk Need to generate the glitch pulse EE 415 VLSI Design

Pulsed Latches EE 415 VLSI Design

Pulsed Latches Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 : EE 415 VLSI Design

Hybrid Latch-FF Timing Data not properly captured due to insufficient hold time EE 415 VLSI Design

Pipelining Reference EE 415 VLSI Design Pipelined

Latch-Based Pipeline EE 415 VLSI Design

Non-Bistable Sequential Circuits─ Schmitt Trigger • VTC with hysteresis • Restores signal slopes EE 415 VLSI Design

Noise Suppression using Schmitt Trigger EE 415 VLSI Design

CMOS Schmitt Trigger VDD M 2 Vin M 4 Vout X M 1 M 3 These transistors resist the change in the X signal Move switching threshold of the first inverter EE 415 VLSI Design

CMOS Schmitt Trigger Increasing kn/kp ratio decreases the logical switching threshold If Vin=0 the Vout (connected to M 4) is also zero So effectively the input is connected to M 2 and M 4 in parallel This increases kp and the switching threshold If Vin=0 the situation is reversed and kn increases reducing the switching threshold EE 415 VLSI Design

Schmitt Trigger Simulated VTC 2. 5 2. 0 Vout(V) VM 1 1. 5 1. 0 VM 2 0. 5 0. 0 k=1 k=2 0. 5 1. 0 1. 5 Vin (V) 2. 0 2. 5 Voltage-transfer characteristics with hysteresis. EE 415 VLSI Design k=3 k=4 0. 0 0. 5 1. 0 1. 5 Vin (V) 2. 0 2. 5 The effect of varying the ratio of the PMOS device M 4. The width is k* 0. 5 m m.

CMOS Schmitt Trigger (2) With input low and output high X is charged to VDD –Vth M 2 is cutoff until the input is larger than VX +Vth With output being pulled down M 5 is cut off and the output transition is very rapid This delays transition from high to low values on the output. Symmetrical analysis can be performed for low to high output transition EE 415 VLSI Design

Multivibrator Circuits EE 415 VLSI Design

Transition-Triggered Monostable In DELAY td EE 415 VLSI Design Out td

Monostable Trigger (RC-based) VDD R In A B Out (a) Trigger circuit. C RC delay regulates the width of the generated pulse In B VM Out t t 1 EE 415 VLSI Design (b) Waveforms. t 2

Astable Multivibrators (Oscillators) EE 415 VLSI Design

Relaxation Oscillator Out 1 I 2 I 1 R C Int T = 2 (log 3) RC EE 415 VLSI Design Out 2

Voltage Controller Oscillator (VCO) VDD M 6 M 4 Schmitt Trigger restores signal slopes M 2 In M 1 Iref Vcontr M 3 M 5 t p. H L (nsec) 4 This effects the delay time 2 EE 415 VLSI Design Current starved inverter Current Iref is a quadratic function of Vcontr 6 0. 0 0. 5 Iref 1. 5 Vcontr (V) 2. 5 propagation delay as a function of control voltage

Differential Delay Element and VCO in 2 V o 1 v 1 in 1 v 2 v 3 v 4 two stage VCO V ctrl delay cell 3. 0 2. 5 V 1 V 2 V 3 V 4 2. 0 1. 5 1. 0 0. 5 0. 0 2 0. 5 1. 5 2. 5 3. 5 time (ns) EE 415 VLSI Design simulated waveforms of 2 -stage VCO

JK- Flip Flop J S Q Q f K R (a) Q Q S R Q Q 1 1 0 1 Q Q 1 0 0 0 0 1 1 1 Jn Kn Qn+1 0 0 1 1 0 1 Qn (c) J f Q K Q (b) For clock=0 S=R=1 and FF maintains its previous state When J=K=1 then S=Q and FF toggles Problem – if JK flip-flop in a toggle state (J=K=1) can flip again For instance when Q=1, and J=K=1, then only R goes low and Q changes to 0. If the clock is still high, the feedback disables K and enables J and FF changes its output again EE 415 VLSI Design

Other Flip-Flops T J f f K Q D J f Q Q K T Q D Q f Q Toggle Flip-Flop EE 415 VLSI Design Delay Flip-Flop (D-latch)

Race Problem tloop t f 1 D Q f Q Signal can race around during f = 1 EE 415 VLSI Design t

Master-Slave Flip-Flop SLAVE MASTER J S Q K R Q SI RI S Q Q R Q Q f PRESET EE 415 VLSI Design J f Q K Q CLEAR Master transmits the signal to the output during the high clock phase and slave is waiting for the clock to change this prevents race conditions