Digital Integrated Circuits A Design Perspective Jan M

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Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction © EE 141 Digital Integrated Circuits 2 nd 1 Introduction

EDA Tools 1)Layout Design Tool 2)SPICE 3)VHDL (synthesis and simulation) © EE 141 Digital

EDA Tools 1)Layout Design Tool 2)SPICE 3)VHDL (synthesis and simulation) © EE 141 Digital Integrated Circuits 2 nd Introduction

1) Layout Editor (Ledit from Tanner EDA tools) Mentor Graphics/Cadence 1) SPICE (ORCAD which

1) Layout Editor (Ledit from Tanner EDA tools) Mentor Graphics/Cadence 1) SPICE (ORCAD which is used in Cadence design tools) 2) VHDL ( Xilinx ISE webpack and Model. Sim, used in cadence, mentor and Synopsis EDA tools) © EE 141 Digital Integrated Circuits 2 nd Introduction

Reference books 1) Digital Integrated Circuits, by: - Jan. M. Rabaey, Anantha Chandrakasan and

Reference books 1) Digital Integrated Circuits, by: - Jan. M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic 1) Principles of CMOS VLSI Design, by: - Niel Weste, Kamran Ishraghian 2) CMOS VLSI Design, by: - Weste-Harris 3) PSPICE using ORCAD, by: - M. H. Rashid 4) VHDL Primer, by: - J. Bhaskar 5) Plenty of material from INTERNET © EE 141 Digital Integrated Circuits 2 nd Introduction

What is this book all about? q Introduction to digital integrated circuits. § CMOS

What is this book all about? q Introduction to digital integrated circuits. § CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies. q What will you learn? § Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability © EE 141 Digital Integrated Circuits 2 nd 5 Introduction

Digital Integrated Circuits Introduction: Issues in digital design q The CMOS inverter q Combinational

Digital Integrated Circuits Introduction: Issues in digital design q The CMOS inverter q Combinational logic structures q Sequential logic gates q Design methodologies q Interconnect: R, L and C q Timing q Arithmetic building blocks q Memories and array structures q © EE 141 Digital Integrated Circuits 2 nd 6 Introduction

Introduction q Why is designing digital ICs different today than it was before? q

Introduction q Why is designing digital ICs different today than it was before? q Will it change in future? © EE 141 Digital Integrated Circuits 2 nd 7 Introduction

The First Computer - use the decimal number system rather than the binary representation

The First Computer - use the decimal number system rather than the binary representation -“store” and “mill” (execute), 2 cycle opn. - used pipelining to speed up the execution of the addition operation -complexity and the cost problem Working part of Babbage’s Difference Engine I (1832), the first known automatic calculator (from [Swade 93], courtesy of the Science Museum of London). © EE 141 Digital Integrated Circuits 2 nd 8 Introduction

Digital Electronics- Era • • Early digital electronics systems were based on magnetically controlled

Digital Electronics- Era • • Early digital electronics systems were based on magnetically controlled switches (or relays). They were mainly used in the implementation of very simple logic networks. Examples of such are train safety systems, where they are still being used at present. The age of digital electronic computing only started in full with the introduction of the vacuum tube. While originally used almost exclusively for analog processing, it was realized early on that the vacuum tube was useful for digital computations as well. © EE 141 Digital Integrated Circuits 2 nd 9 Introduction

ENIAC - The first electronic computer (1946) - vacuum tube based computer - UNIVAC

ENIAC - The first electronic computer (1946) - vacuum tube based computer - UNIVAC I (the first successful commercial computer) -Integration Density: 80 feet long, 8. 5 feet high and several feet wide and incorporated 18, 000 vacuum tubes. - Reliability problems and excessive power consumption made the implementation of larger engines economically and practically infeasible. © EE 141 Digital Integrated Circuits 2 nd 10 Introduction

The Transistor Revolution invention of the transistor at Bell Telephone Laboratories in 1947 [

The Transistor Revolution invention of the transistor at Bell Telephone Laboratories in 1947 [ Bardeen], followed by the introduction of the bipolar transistor by Schockley in 1949 [Schockley] First transistor Bell Labs, 1948 © EE 141 Digital Integrated Circuits 2 nd 11 Introduction

The First Integrated Circuits Bipolar logic 1960’s ECL 3 -input Gate Motorola 1966 -

The First Integrated Circuits Bipolar logic 1960’s ECL 3 -input Gate Motorola 1966 - TTL had the advantage, however, of offering a higher integration density and was the basis of the first integrated circuit revolution. -In fact, the manufacturing of TTL components is what spear-headed the first large semiconductor companies such as Fair-child, National, and Texas Instruments. - The family was so successful that it composed the largest fraction of the digital semiconductor market until the 1980 s. © EE 141 Digital Integrated Circuits 2 nd 12 Introduction

 • Ultimately, bipolar digital logic lost the battle for hegemony in the digital

• Ultimately, bipolar digital logic lost the battle for hegemony in the digital design world for exactly the reasons that haunted the vacuum tube approach. • The large power consumption per gate puts an upper limit on the number of gates that can be reliably integrated on a single die, package, housing, or box. • Although attempts were made to develop high integration density, lowpower bipolar families (such as I 2 L—Integrated Injection Logic [Hart 72]). • The torch was gradually passed to the MOS digital integrated circuit approach. © EE 141 Digital Integrated Circuits 2 nd 13 Introduction

MOS Device issues • The basic principle behind the MOSFET transistor (originally called IGFET)

MOS Device issues • The basic principle behind the MOSFET transistor (originally called IGFET) was proposed in a patent by J. Lilienfeld (Canada) as early as 1925, and, independently, by O. Heil in England in 1935. • Insufficient knowledge of the materials and gate stability problems, however, delayed the practical usability of the device for a long time. Once these were solved, MOS digital integrated circuits started to take off in full in the early 1970 s. • The complexity of the manufacturing process delayed the full exploitation of these devices for two more decades. • The first practical MOS integrated circuits were implemented in PMOSonly logic and were used in applications such as calculators. The second age of the digital integrated circuit revolution was inaugurated with the introduction of the first microprocessors by Intel in 1972 (the 4004) and 1974 (the 8080). © EE 141 Digital Integrated Circuits 2 nd 14 Introduction

Intel 4004 Micro-Processor First 4 Kbit MOS memory : 1970 1971 1000 transistors 1

Intel 4004 Micro-Processor First 4 Kbit MOS memory : 1970 1971 1000 transistors 1 MHz operation Handcrafted These processors were implemented in NMOSonly logic, which has the advantage of higher speed over the PMOS logic. © EE 141 Digital Integrated Circuits 2 nd 15 Introduction

 • These events were at the start of a truly astounding evolution towards

• These events were at the start of a truly astounding evolution towards ever higher integration densities and speed performances, a revolution that is still in full swing right now. • In the late 1970 s, NMOS-only logic started to suffer from the same plague that made high-density bipolar logic unattractive or infeasible: power consumption. • This requirement, combined with progress in manufacturing technology, finally tilted the balance towards the CMOS technology, and this is where we still are today. © EE 141 Digital Integrated Circuits 2 nd 16 Introduction

Intel Pentium (IV) microprocessor year 2000 ~40 million transistors Hierarchical approach © EE 141

Intel Pentium (IV) microprocessor year 2000 ~40 million transistors Hierarchical approach © EE 141 Digital Integrated Circuits 2 nd 17 Introduction

 • Interestingly enough, power consumption concerns are rapidly becoming dominant in CMOS design

• Interestingly enough, power consumption concerns are rapidly becoming dominant in CMOS design as well, and this time there does not seem to be a new technology around the corner to alleviate the problem. • Although the large majority of current ICs are implemented in the MOS technology, other technologies come into play when very high performance is at stake. • An example of this is the Bi. CMOS : bipolar and MOS devices on the same die. Bi. CMOS is used in high-speed memories and gate arrays. © EE 141 Digital Integrated Circuits 2 nd 18 Introduction

 • When even higher performance is necessary, other technologies emerge besides the bipolar

• When even higher performance is necessary, other technologies emerge besides the bipolar silicon ECL family— Gallium-Arsenide, Silicon-Germanium and even superconducting technologies. • These technologies only play a very small role in the overall digital integrated circuit design scene. With the ever increasing performance of CMOS, this role is bound to be further reduced with time. © EE 141 Digital Integrated Circuits 2 nd 19 Introduction

Moore’s Law (amazing visionary) l. In 1965, Gordon Moore noted that the number of

Moore’s Law (amazing visionary) l. In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. l. He made a prediction that semiconductor technology will double its effectiveness every 18 months * Integration density and performance of integrated circuits have gone through an astounding revolution in the last couple of decades. © EE 141 Digital Integrated Circuits 2 nd 20 Introduction

Moore’s Law Electronics, April 19, 1965. © EE 141 Digital Integrated Circuits 2 nd

Moore’s Law Electronics, April 19, 1965. © EE 141 Digital Integrated Circuits 2 nd 21 Introduction

Evolution in Memory Complexity As can be observed, integration complexity doubles approximately every 1

Evolution in Memory Complexity As can be observed, integration complexity doubles approximately every 1 to 2 years. As a result, memory density has increased by more than a thousandfold since 1970. © EE 141 Digital Integrated Circuits 2 nd 22 Introduction

Transistor Counts 1 Billion Transistors K 1, 000 100, 000 1, 000 i 386

Transistor Counts 1 Billion Transistors K 1, 000 100, 000 1, 000 i 386 80286 100 10 i 486 Pentium® III Pentium® Pro Pentium® 8086 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected © EE 141 Digital Integrated Circuits 2 nd Courtesy, Intel 23 Introduction

Moore’s law in Microprocessors Transistors (MT) 1000 2 X growth in 1. 96 years!

Moore’s law in Microprocessors Transistors (MT) 1000 2 X growth in 1. 96 years! 100 10 486 1 P 6 Pentium® proc 386 286 0. 1 8086 8080 8008 4004 8085 Transistors on Lead Microprocessors double every 2 years 0. 01 0. 001 1970 © EE 141 Digital Integrated 1980 Circuits 2 nd 1990 Year Courtesy, Intel 2000 2010 24 Introduction

Die Size Growth Die size (mm) 100 10 8080 8008 4004 1 1970 8086

Die Size Growth Die size (mm) 100 10 8080 8008 4004 1 1970 8086 8085 1980 286 386 P 6 Pentium ® proc 486 ~7% growth per year ~2 X growth in 10 years 1990 Year 2000 2010 Die size grows by 14% to satisfy Moore’s Law © EE 141 Digital Integrated Circuits 2 nd Courtesy, Intel 25 Introduction

Frequency (Mhz) 10000 Doubles every 2 years 1000 10 8085 1 0. 1 1970

Frequency (Mhz) 10000 Doubles every 2 years 1000 10 8085 1 0. 1 1970 8086 286 386 486 P 6 Pentium ® proc 8080 8008 4004 1980 1990 Year 2000 2010 Lead Microprocessors frequency doubles every 2 years © EE 141 Digital Integrated Circuits 2 nd Courtesy, Intel 26 Introduction

Power Dissipation Power (Watts) 100 P 6 Pentium ® proc 10 8086 286 1

Power Dissipation Power (Watts) 100 P 6 Pentium ® proc 10 8086 286 1 8008 4004 486 386 8085 8080 0. 1 1974 1978 1985 1992 2000 Year Lead Microprocessors power continues to increase © EE 141 Digital Integrated Circuits 2 nd Courtesy, Intel 27 Introduction

Power will be a major problem 100000 18 KW 5 KW 1. 5 KW

Power will be a major problem 100000 18 KW 5 KW 1. 5 KW 500 W Power (Watts) 10000 1000 Pentium® proc 100 286 486 8086 10 386 8085 8080 8008 1 4004 0. 1 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive © EE 141 Digital Integrated Circuits 2 nd Courtesy, Intel 28 Introduction

Power density Power Density (W/cm 2) 10000 Rocket Nozzle 1000 Nuclear Reactor 100 8086

Power density Power Density (W/cm 2) 10000 Rocket Nozzle 1000 Nuclear Reactor 100 8086 10 4004 Hot Plate P 6 8008 8085 Pentium® proc 386 286 486 8080 1 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp © EE 141 Digital Integrated Circuits 2 nd Courtesy, Intel 29 Introduction

Not Only Microprocessors Cell Phone Small Signal RF Digital Cellular Market (Phones Shipped) Power

Not Only Microprocessors Cell Phone Small Signal RF Digital Cellular Market (Phones Shipped) Power RF Power Management 1996 1997 1998 1999 2000 Units 48 M 86 M 162 M 260 M 435 M Analog Baseband Digital Baseband (DSP + MCU) (data from Texas Instruments) © EE 141 Digital Integrated Circuits 2 nd 30 Introduction

Challenges in Digital Design µ DSM µ 1/DSM “Macroscopic Issues” “Microscopic Problems” • Time-to-Market

Challenges in Digital Design µ DSM µ 1/DSM “Macroscopic Issues” “Microscopic Problems” • Time-to-Market • Millions of Gates • High-Level Abstractions • Reuse & IP: Portability • Predictability • etc. • Ultra-high speed design • Interconnect • Noise, Crosstalk • Reliability, Manufacturability • Power Dissipation • Clock distribution. Everything Looks a Little Different ? © EE 141 Digital Integrated Circuits 2 nd …and There’s a Lot of Them! 31 Introduction

10, 000 100, 000, 000 Logic Tr. /Chip Tr. /Staff Month. 1, 000, 000

10, 000 100, 000, 000 Logic Tr. /Chip Tr. /Staff Month. 1, 000, 000 10, 000 100, 000 Productivity (K) Trans. /Staff - Mo. Complexity Logic Transistor per Chip (M) Productivity Trends 1, 000, 000 58%/Yr. compounded Complexity growth rate 10 10, 000 100, 000 1, 0001 10 10, 000 x 0. 1 100 xx 0. 01 10 xx x x 1 1, 000 21%/Yr. compound Productivity growth rate x 0. 1 100 0. 01 10 2009 2007 2005 2003 2001 1999 1997 1995 1993 1991 1989 1987 1985 1983 1981 0. 001 1 Source: Sematech Complexity outpaces design productivity © EE 141 Digital Integrated Circuits 2 nd Courtesy, ITRS Roadmap 32 Introduction

Why Scaling? Technology shrinks by 0. 7/generation q With every generation can integrate 2

Why Scaling? Technology shrinks by 0. 7/generation q With every generation can integrate 2 x more functions per chip; chip cost does not increase significantly q Cost of a function decreases by 2 x q But … q § How to design chips with more and more functions? § Design engineering population does not double every two years… q Hence, a need for more efficient design methods § Exploit different levels of abstraction © EE 141 Digital Integrated Circuits 2 nd 33 Introduction

(black box) SYSTEM MODULE + GATE CIRCUIT DEVICE G S n+ D n+ Cells

(black box) SYSTEM MODULE + GATE CIRCUIT DEVICE G S n+ D n+ Cells are reused as much as possible to reduce the design effort and to enhance the chances for a first-time-right implementation. ‘DESIGN COMPLEXITY’ can be reduced. © EE 141 Digital Integrated Circuits 2 nd 34 Introduction

The crucial concept here is abstraction. At each design level, the internal details of

The crucial concept here is abstraction. At each design level, the internal details of a complex module can be abstracted away and replaced by a black box view or model. This model contains virtually all the information needed to deal with the block at the next level of hierarchy. For all purposes, it can hence be considered a black box with known characteristics. As there exists no compelling need for the system designer to look inside this box, design complexity is substantially reduced. For instance, an AND gate is adequately described by its Boolean expression (Z = A. B), its bounding box, the position of the input and output terminals, and the delay between the inputs and the output. This is analogous to a software designer using a library of software routines such as input/output drivers. Someone writing a large program does not bother to look inside those library routines. The only thing he cares about is the intended result of calling one of those modules. (CAD) frameworks for digital integrated circuits; without it the current design complexity would not have been achievable. Design tools include simulation at the various complexity levels, design verification, layout generation, and design synthesis. © EE 141 Digital Integrated Circuits 2 nd 35 Introduction

 • The preceding analysis demonstrates that design automation and modular design practices have

• The preceding analysis demonstrates that design automation and modular design practices have effectively addressed some of the complexity issues incurred in contemporary digital design. This leads to the following pertinent question. If design automation solves all our design problems, why should we be concerned with digital circuit design at all? • Will the next-generation digital designer ever have to worry about transistors or parasitics, or is the smallest design entity he will ever consider the gate and the module? • The truth is that the reality is more complex, and various reasons exist as to why an insight into digital circuits and their intricacies will still be an important asset for a long time to come : © EE 141 Digital Integrated Circuits 2 nd 36 Introduction

 • First of all, someone still has to design and implement the module

• First of all, someone still has to design and implement the module libraries. Semiconductor technologies continue to advance from year to year. Until one has developed a fool-proof approach towards “porting” a cell from one technology to another, each change in technology—which happens approximately every two years—requires a redesign of the library. • Creating an adequate model of a cell or module requires an in-depth understanding of its internal operation. For instance, to identify the dominant performance parameters of a given design, one has to recognize the critical timing path first. © EE 141 Digital Integrated Circuits 2 nd 37 Introduction

 • The library-based approach works fine when the design constraints (speed, cost or

• The library-based approach works fine when the design constraints (speed, cost or power) are not stringent. Unfortunately for a large number of other products such as microprocessors, success hinges on high performance, and designers therefore tend to push technology to its limits. At that point, the hierarchical approach tends to become somewhat less attractive. To resort to our previous analogy to software methodologies, a programmer tends to “customize” software routines when execution speed is crucial; compilers—or design tools— are not yet to the level of what human sweat or ingenuity can deliver. • Even more important is the observation that the abstraction-based approach is only correct to a certain degree. The performance of, for instance, an adder can be substantially influenced by the way it is connected to its environment. The interconnection wires themselves contribute to delay as they introduce parasitic capacitances, resistances and even inductances. The impact of the interconnect parasitics is bound to increase in the years to come with the scaling of the technology. © EE 141 Digital Integrated Circuits 2 nd 38 Introduction

 • Scaling tends to emphasize some other deficiencies of the abstraction-based model. Some

• Scaling tends to emphasize some other deficiencies of the abstraction-based model. Some design entities tend to be global or external. Examples of global factors are the clock signals, used for synchronization in a digital design, and the supply lines. Increasing the size of a digital design has a profound effect on these global signals. For instance, connecting more cells to a supply line can cause a voltage drop over the wire, which, in its turn, can slow down all the connected cells. Issues such as clock distribution, circuit synchronization, and supplyvoltage distribution are becoming more and more critical. Coping with them requires a profound understanding of the intricacies of digital circuit design. © EE 141 Digital Integrated Circuits 2 nd 39 Introduction

 • Another impact of technology evolution is that new design issues and constraints

• Another impact of technology evolution is that new design issues and constraints tend to emerge over time. A typical example of this is the periodical reemergence of power dissipation as a constraining factor, as was already illustrated in the historical overview. Another example is the changing ratio between device and interconnect parasitics. To cope with these unforeseen factors, one must at least be able to model and analyze their impact, requiring once again a profound insight into circuit topology and behavior. • Finally, when things can go wrong, they do. A fabricated circuit does not always exhibit the exact waveforms one might expect from advance simulations. Deviations can be caused by variations in the fabrication process parameters, or by the inductance of the package, or by a badly modeled clock signal. Troubleshooting a design requires circuit expertise. © EE 141 Digital Integrated Circuits 2 nd 40 Introduction

Design Metrics q How to evaluate performance of a digital circuit (gate, block, …)?

Design Metrics q How to evaluate performance of a digital circuit (gate, block, …)? § § Cost Reliability (Noise) Scalability Speed (delay, operating frequency of micro processors) § Power dissipation § Energy to perform a function (mobiles) © EE 141 Digital Integrated Circuits 2 nd 41 Introduction

Cost of Integrated Circuits q NRE/fixed (non-recurrent engineering) costs § design time and effort,

Cost of Integrated Circuits q NRE/fixed (non-recurrent engineering) costs § design time and effort, mask generation § one-time cost factor, independent of the sales volume, the number of products sold q Recurrent costs/variable § silicon processing, packaging, test § proportional to products volume § proportional to chip area © EE 141 Digital Integrated Circuits 2 nd 42 Introduction

NRE Cost is Increasing © EE 141 Digital Integrated Circuits 2 nd 43 Introduction

NRE Cost is Increasing © EE 141 Digital Integrated Circuits 2 nd 43 Introduction

Die Cost Single die Wafer Going up to 12” (30 cm) From http: //www.

Die Cost Single die Wafer Going up to 12” (30 cm) From http: //www. amd. com © EE 141 Digital Integrated Circuits 2 nd 44 Introduction

Cost per Transistor cost: ¢-per-transistor 1 0. 1 Fabrication capital cost per transistor (Moore’s

Cost per Transistor cost: ¢-per-transistor 1 0. 1 Fabrication capital cost per transistor (Moore’s la 0. 01 0. 0001 0. 000001 0. 0000001 1982 1985 © EE 141 Digital Integrated 1988 Circuits 2 nd 1991 1994 1997 2000 2003 2006 2009 45 2012 Introduction

Yield © EE 141 Digital Integrated Circuits 2 nd 46 Introduction

Yield © EE 141 Digital Integrated Circuits 2 nd 46 Introduction

Defects a is approximately 3 The smaller the gate, the higher the integration density

Defects a is approximately 3 The smaller the gate, the higher the integration density and the smaller the die size. Smaller gates furthermore tend to be faster and consume less energy, as the total gate capacitance which is one of the dominant performance parameters often scales with the area. © EE 141 Digital Integrated Circuits 2 nd 47 Introduction

Some Examples (1994) Chip Metal Line layers width Wafer cost Def. / Area Dies/

Some Examples (1994) Chip Metal Line layers width Wafer cost Def. / Area Dies/ Yield cm 2 mm 2 wafer Die cost 386 DX 2 0. 90 $900 1. 0 43 360 71% $4 486 DX 2 3 0. 80 $1200 1. 0 81 181 54% $12 Power PC 601 4 0. 80 $1700 1. 3 121 115 28% $53 HP PA 7100 3 0. 80 $1300 1. 0 196 66 27% $73 DEC Alpha 3 0. 70 $1500 1. 2 234 53 19% $149 Super Sparc 3 0. 70 $1700 1. 6 256 48 13% $272 Pentium 3 0. 80 $1500 1. 5 296 40 9% $417 © EE 141 Digital Integrated Circuits 2 nd 48 Introduction

Reliability― Noise in Digital Integrated Circuits v(t) i(t) Inductive coupling © EE 141 Digital

Reliability― Noise in Digital Integrated Circuits v(t) i(t) Inductive coupling © EE 141 Digital Integrated Circuits 2 nd Capacitive coupling V DD Power and ground noise 49 Introduction

DC Operation Voltage Transfer Characteristic V(y) V VOH = f(VOL) VOL = f(VOH) VM

DC Operation Voltage Transfer Characteristic V(y) V VOH = f(VOL) VOL = f(VOH) VM = f(VM) f OH V(y)=V(x) VM Switching Threshold V OL V IH V(x) Nominal Voltage Levels © EE 141 Digital Integrated Circuits 2 nd 50 Introduction

Mapping between analog and digital signals V “ 1” V OH V IH Transition

Mapping between analog and digital signals V “ 1” V OH V IH Transition Width (TW) OH Slope = -1 Undefined Region V “ 0” V out V Slope = -1 IL V OL OL V © EE 141 Digital Integrated Circuits 2 nd IL V IH V in 51 Introduction

Definition of Noise Margins Robust, insensitive to noises "1" V V OH NM L

Definition of Noise Margins Robust, insensitive to noises "1" V V OH NM L OL V Noise margin high IH V Undefined Region IL Noise margin low "0" Gate Output Stage M © EE 141 Digital Integrated Circuits 2 nd Gate Input Stage M+1 52 Introduction

© EE 141 Digital Integrated Circuits 2 nd Introduction

© EE 141 Digital Integrated Circuits 2 nd Introduction

Regenerative Property v 0 v 1 v 2 Regenerative After passing a no. of

Regenerative Property v 0 v 1 v 2 Regenerative After passing a no. of stages © EE 141 Digital Integrated Circuits 2 nd v 3 v 4 v 5 v 6 Non-Regenerative The difference is due to 54 the gain char. Of gates Introduction

Regenerative Property v 0 v 1 v 2 v 3 v 4 v 5

Regenerative Property v 0 v 1 v 2 v 3 v 4 v 5 v 6 A chain of inverters Simulated response © EE 141 Digital Integrated Circuits 2 nd 55 Introduction

A gate has Regenerative property q VTC should have a transient region with gain

A gate has Regenerative property q VTC should have a transient region with gain greater than 1, bordered by two legal zones where the gain should be less than 1. Vout VOH Slope = -1 VOL © EE 141 Digital Integrated VIL VIH Circuits 2 nd Vin 56 Introduction

Fan-in and Fan-out N © EE 141 Digital Integrated Circuits 2 nd M Fan-in

Fan-in and Fan-out N © EE 141 Digital Integrated Circuits 2 nd M Fan-in M 57 Introduction

The Ideal Gate V out Ri = Ro = 0 Fanout = NMH =

The Ideal Gate V out Ri = Ro = 0 Fanout = NMH = NML = VDD/2 g= V in © EE 141 Digital Integrated Circuits 2 nd 58 Introduction

An Old-time Inverter 5. 0 4. 0 NM L 3. 0 (V) 2. 0

An Old-time Inverter 5. 0 4. 0 NM L 3. 0 (V) 2. 0 out V VM NM H 1. 0 0. 0 © EE 141 Digital Integrated 1. 0 Circuits 2 nd 2. 0 3. 0 V in (V) 4. 0 59 Introduction

VOH=3. 5 V ; VOL = 0. 45 V VIH = 2. 35 V

VOH=3. 5 V ; VOL = 0. 45 V VIH = 2. 35 V ; VIL = 0. 66 V VM= 1. 64 V ; NMH = 1. 15 V ; NML = 0. 21 V © EE 141 Digital Integrated Circuits 2 nd 60 Introduction

Delay Definitions tp: propagation delay of gate tp= (tp. HL+tp. LH)/2 © EE 141

Delay Definitions tp: propagation delay of gate tp= (tp. HL+tp. LH)/2 © EE 141 Digital Integrated Circuits 2 nd 61 Introduction

Assignment-1 (due on August 10 th) tp= (tp. HL+tp. LH)/2 Find the propagation delay

Assignment-1 (due on August 10 th) tp= (tp. HL+tp. LH)/2 Find the propagation delay of an inverter PMOS: W=15 u L=2. 5 u ; NMOS: W=5 u L=2. 5 u - Vdd=5 Volts - Input at the gate is a pulse with following specifications: initial voltage=0; peak voltage=5 V; initial delay time=0; rise time=5 ns; fall time=5 ns; pulse-width=48 ns; and Period=120 ns, q - Consider Level 2 MOSFET model Consider load capacitance CL=100 f. F at the output. Submit your assignments via e-mail to: svenitk@gmail. com © EE 141 Digital Integrated Circuits 2 nd Introduction

A First-Order RC Network R vin vout C tp = ln (2) t =

A First-Order RC Network R vin vout C tp = ln (2) t = 0. 69 RC Important model – matches delay of inverter The time to reach the 50% point is easily computed as t = ln(2) t = 0. 69 t. Similarly, it takes t= ln(9) t = 2. 2 t to get to the 90% point. © EE 141 Digital Integrated Circuits 2 nd 63 Introduction

Power Dissipation Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t) Peak power (supply line size):

Power Dissipation Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t) Peak power (supply line size): Ppeak = Vsupplyipeak Average power (Battery Size): Pave : Static and Dynamic © EE 141 Digital Integrated Circuits 2 nd 64 Introduction

Energy and Energy-Delay Power-Delay Product (PDP) = Energy per operation = Pav tp The

Energy and Energy-Delay Power-Delay Product (PDP) = Energy per operation = Pav tp The PDP is simply the energy consumed by the gate per switching event. Energy-Delay Product (EDP) = quality metric of gate = E tp © EE 141 Digital Integrated Circuits 2 nd 65 Introduction

A First-Order RC Network R vin © EE 141 Digital Integrated Circuits 2 nd

A First-Order RC Network R vin © EE 141 Digital Integrated Circuits 2 nd vout CL 66 Introduction

Summary Digital integrated circuits have come a long way and still have quite some

Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades q Some interesting challenges ahead q § Getting a clear perspective on the challenges and potential solutions is the purpose of this book q Understanding the design metrics that govern digital design is crucial § Cost, reliability, speed, power and energy dissipation © EE 141 Digital Integrated Circuits 2 nd 67 Introduction