Digital Integrated Circuits A Design Perspective Jan M

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 © EE 141 Digital Integrated Circuits 2 nd 1 Introduction

What is this book all about? q Introduction to digital integrated circuits. § CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies. q What will you learn? § Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability © EE 141 Digital Integrated Circuits 2 nd 2 Introduction

Digital Integrated Circuits Introduction: Issues in digital design q The CMOS inverter q Combinational logic structures q Sequential logic gates q Design methodologies q Interconnect: R, L and C q Timing q Arithmetic building blocks q Memories and array structures q © EE 141 Digital Integrated Circuits 2 nd 3 Introduction

Introduction q Why is designing digital ICs different today than it was before? q Will it change in future? © EE 141 Digital Integrated Circuits 2 nd 4 Introduction

The First Computer © EE 141 Digital Integrated Circuits 2 nd 5 Introduction

ENIAC - The first electronic computer (1946) © EE 141 Digital Integrated Circuits 2 nd 6 Introduction

The Transistor Revolution First transistor Bell Labs, 1948 © EE 141 Digital Integrated Circuits 2 nd 7 Introduction

The First Integrated Circuits Bipolar logic 1960’s ECL 3 -input Gate Motorola 1966 © EE 141 Digital Integrated Circuits 2 nd 8 Introduction

Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation © EE 141 Digital Integrated Circuits 2 nd 9 Introduction

Intel Pentium (IV) microprocessor © EE 141 Digital Integrated Circuits 2 nd 10 Introduction

Moore’s Law l. In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. l. He made a prediction that semiconductor technology will double its effectiveness every 18 months © EE 141 Digital Integrated Circuits 2 nd 11 Introduction

Moore’s Law Electronics, April 19, 1965. © EE 141 Digital Integrated Circuits 2 nd 12 Introduction

Evolution in Complexity © EE 141 Digital Integrated Circuits 2 nd 13 Introduction

Transistor Counts 1 Billion Transistors K 1, 000 100, 000 1, 000 i 386 80286 100 10 i 486 Pentium® III Pentium® Pro Pentium® 8086 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected © EE 141 Digital Integrated Circuits 2 nd Courtesy, Intel 14 Introduction

Moore’s law in Microprocessors Transistors (MT) 1000 2 X growth in 1. 96 years! 100 10 486 1 P 6 Pentium® proc 386 286 0. 1 8086 8080 8008 4004 8085 Transistors on Lead Microprocessors double every 2 years 0. 01 0. 001 1970 © EE 141 Digital Integrated 1980 Circuits 2 nd 1990 Year Courtesy, Intel 2000 2010 15 Introduction

Die Size Growth Die size (mm) 100 10 8080 8008 4004 1 1970 8086 8085 1980 286 386 P 6 Pentium ® proc 486 ~7% growth per year ~2 X growth in 10 years 1990 Year 2000 2010 Die size grows by 14% to satisfy Moore’s Law © EE 141 Digital Integrated Circuits 2 nd Courtesy, Intel 16 Introduction

Frequency (Mhz) 10000 Doubles every 2 years 1000 10 8085 1 0. 1 1970 8086 286 386 486 P 6 Pentium ® proc 8080 8008 4004 1980 1990 Year 2000 2010 Lead Microprocessors frequency doubles every 2 years © EE 141 Digital Integrated Circuits 2 nd Courtesy, Intel 17 Introduction

Power Dissipation Power (Watts) 100 P 6 Pentium ® proc 10 8086 286 1 8008 4004 486 386 8085 8080 0. 1 1974 1978 1985 1992 2000 Year Lead Microprocessors power continues to increase © EE 141 Digital Integrated Circuits 2 nd Courtesy, Intel 18 Introduction

Power will be a major problem 100000 18 KW 5 KW 1. 5 KW 500 W Power (Watts) 10000 1000 Pentium® proc 100 286 486 8086 10 386 8085 8080 8008 1 4004 0. 1 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive © EE 141 Digital Integrated Circuits 2 nd Courtesy, Intel 19 Introduction

Power density Power Density (W/cm 2) 10000 Rocket Nozzle 1000 Nuclear Reactor 100 8086 10 4004 Hot Plate P 6 8008 8085 Pentium® proc 386 286 486 8080 1 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp © EE 141 Digital Integrated Circuits 2 nd Courtesy, Intel 20 Introduction

Not Only Microprocessors Cell Phone Small Signal RF Digital Cellular Market (Phones Shipped) Power RF Power Management 1996 1997 1998 1999 2000 Units 48 M 86 M 162 M 260 M 435 M Analog Baseband Digital Baseband (DSP + MCU) (data from Texas Instruments) © EE 141 Digital Integrated Circuits 2 nd 21 Introduction

Challenges in Digital Design µ DSM µ 1/DSM “Macroscopic Issues” “Microscopic Problems” • Time-to-Market • Millions of Gates • High-Level Abstractions • Reuse & IP: Portability • Predictability • etc. • Ultra-high speed design • Interconnect • Noise, Crosstalk • Reliability, Manufacturability • Power Dissipation • Clock distribution. Everything Looks a Little Different ? © EE 141 Digital Integrated Circuits 2 nd …and There’s a Lot of Them! 22 Introduction

10, 000 100, 000, 000 Logic Tr. /Chip Tr. /Staff Month. 1, 000, 000 10, 000 100, 000 Productivity (K) Trans. /Staff - Mo. Complexity Logic Transistor per Chip (M) Productivity Trends 1, 000, 000 58%/Yr. compounded Complexity growth rate 10 10, 000 100, 000 1, 0001 10 10, 000 x 0. 1 100 xx 0. 01 10 xx x x 1 1, 000 21%/Yr. compound Productivity growth rate x 0. 1 100 0. 01 10 2009 2007 2005 2003 2001 1999 1997 1995 1993 1991 1989 1987 1985 1983 1981 0. 001 1 Source: Sematech Complexity outpaces design productivity © EE 141 Digital Integrated Circuits 2 nd Courtesy, ITRS Roadmap 23 Introduction

Why Scaling? Technology shrinks by 0. 7/generation q With every generation can integrate 2 x more functions per chip; chip cost does not increase significantly q Cost of a function decreases by 2 x q But … q § How to design chips with more and more functions? § Design engineering population does not double every two years… q Hence, a need for more efficient design methods § Exploit different levels of abstraction © EE 141 Digital Integrated Circuits 2 nd 24 Introduction

Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT DEVICE G S n+ © EE 141 Digital Integrated Circuits 2 nd D n+ 25 Introduction

Design Metrics q How to evaluate performance of a digital circuit (gate, block, …)? § § § Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function © EE 141 Digital Integrated Circuits 2 nd 26 Introduction

Cost of Integrated Circuits q NRE (non-recurrent engineering) costs § design time and effort, mask generation § one-time cost factor q Recurrent costs § silicon processing, packaging, test § proportional to volume § proportional to chip area © EE 141 Digital Integrated Circuits 2 nd 27 Introduction

NRE Cost is Increasing © EE 141 Digital Integrated Circuits 2 nd 28 Introduction

Die Cost Single die Wafer Going up to 12” (30 cm) From http: //www. amd. com © EE 141 Digital Integrated Circuits 2 nd 29 Introduction

Cost per Transistor cost: ¢-per-transistor 1 0. 1 Fabrication capital cost per transistor (Moore’s la 0. 01 0. 0001 0. 000001 0. 0000001 1982 1985 © EE 141 Digital Integrated 1988 Circuits 2 nd 1991 1994 1997 2000 2003 2006 2009 30 2012 Introduction

Yield © EE 141 Digital Integrated Circuits 2 nd 31 Introduction

Defects a is approximately 3 © EE 141 Digital Integrated Circuits 2 nd 32 Introduction

Some Examples (1994) Chip Metal Line layers width Wafer cost Def. / Area Dies/ Yield cm 2 mm 2 wafer Die cost 386 DX 2 0. 90 $900 1. 0 43 360 71% $4 486 DX 2 3 0. 80 $1200 1. 0 81 181 54% $12 Power PC 601 4 0. 80 $1700 1. 3 121 115 28% $53 HP PA 7100 3 0. 80 $1300 1. 0 196 66 27% $73 DEC Alpha 3 0. 70 $1500 1. 2 234 53 19% $149 Super Sparc 3 0. 70 $1700 1. 6 256 48 13% $272 Pentium 3 0. 80 $1500 1. 5 296 40 9% $417 © EE 141 Digital Integrated Circuits 2 nd 33 Introduction

Reliability― Noise in Digital Integrated Circuits v(t) i(t) Inductive coupling © EE 141 Digital Integrated Circuits 2 nd Capacitive coupling V DD Power and ground noise 34 Introduction

DC Operation Voltage Transfer Characteristic V(y) V VOH = f(VOL) VOL = f(VOH) VM = f(VM) f OH V(y)=V(x) VM Switching Threshold V OL V OH V(x) Nominal Voltage Levels © EE 141 Digital Integrated Circuits 2 nd 35 Introduction

Mapping between analog and digital signals V “ 1” V OH V IH V out OH Slope = -1 Undefined Region V “ 0” V Slope = -1 IL V OL OL V © EE 141 Digital Integrated Circuits 2 nd IL V IH V in 36 Introduction

Definition of Noise Margins "1" V V OH NM L OL V Noise margin high IH V Undefined Region IL Noise margin low "0" Gate Output © EE 141 Digital Integrated Circuits 2 nd Gate Input 37 Introduction

Noise Budget q Allocates gross noise margin to expected sources of noise q Sources: supply noise, cross talk, interference, offset q Differentiate between fixed and proportional noise sources © EE 141 Digital Integrated Circuits 2 nd 38 Introduction

Key Reliability Properties q Absolute noise margin values are deceptive § a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) q Noise immunity is the more important metric – the capability to suppress noise sources q Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver; © EE 141 Digital Integrated Circuits 2 nd 39 Introduction

Regenerative Property Regenerative © EE 141 Digital Integrated Circuits 2 nd Non-Regenerative 40 Introduction

Regenerative Property v 0 v 1 v 2 v 3 v 4 v 5 v 6 A chain of inverters Simulated response © EE 141 Digital Integrated Circuits 2 nd 41 Introduction

Fan-in and Fan-out N © EE 141 Digital Integrated Circuits 2 nd M Fan-in M 42 Introduction

The Ideal Gate V out Ri = Ro = 0 Fanout = NMH = NML = VDD/2 g= V in © EE 141 Digital Integrated Circuits 2 nd 43 Introduction

An Old-time Inverter 5. 0 4. 0 NM L 3. 0 (V) 2. 0 out V VM NM H 1. 0 0. 0 © EE 141 Digital Integrated 1. 0 Circuits 2 nd 2. 0 3. 0 V in (V) 4. 0 5. 0 44 Introduction

Delay Definitions © EE 141 Digital Integrated Circuits 2 nd 45 Introduction

Ring Oscillator T = 2 ´ tp ´ N © EE 141 Digital Integrated Circuits 2 nd 46 Introduction

A First-Order RC Network R vin vout C tp = ln (2) t = 0. 69 RC Important model – matches delay of inverter © EE 141 Digital Integrated Circuits 2 nd 47 Introduction

Power Dissipation Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t) Peak power: Ppeak = Vsupplyipeak Average power: © EE 141 Digital Integrated Circuits 2 nd 48 Introduction

Energy and Energy-Delay Power-Delay Product (PDP) = Energy per operation = Pav tp Energy-Delay Product (EDP) = quality metric of gate = E tp © EE 141 Digital Integrated Circuits 2 nd 49 Introduction

A First-Order RC Network R vin © EE 141 Digital Integrated Circuits 2 nd vout CL 50 Introduction

Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades q Some interesting challenges ahead q § Getting a clear perspective on the challenges and potential solutions is the purpose of this book q Understanding the design metrics that govern digital design is crucial § Cost, reliability, speed, power and energy dissipation © EE 141 Digital Integrated Circuits 2 nd 51 Introduction