Digital Integrated Circuits A Design Perspective Jan M
- Slides: 41
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Design Methodologies © Digital Integrated Circuits 2 nd Design Methodologie
The Design Productivity Challenge A growing gap between design complexity and design productivity Source: sematech 97 © Digital Integrated Circuits 2 nd Design Methodologie
A Simple Processor INPUT/OUTPUT MEMORY CONTROL INPUT-OUTPUT DATAPATH The structure may be repeated many times on a single die (SOC) © Digital Integrated Circuits 2 nd Design Methodologie
Datapath: 1) All computations are performed here 2) Consists of an interconnection of basic combinational functions, such as logic (AND, OR etc) or arithmetic operators (addition, multiplication etc) Control Module: 1) Determines what actions happen in the processor at any given time. It can be viewed as a state machine (FSM) © Digital Integrated Circuits 2 nd Design Methodologie
A System-on-a-Chip: Example Courtesy: Philips Combines all the functions needed for the realization of a complete high-definition digital TV set (It combines two processors here) © Digital Integrated Circuits 2 nd Design Methodologie
None Configurable/Parameterizable 10 -100 Hardwired custom Energy Efficiency (in MOPS/m. W) 100 -1000 1 -10 Embedded microprocessor Domain-specific processor (e. g. DSP) Impact of Implementation Choices 0. 1 -1 Somewhat flexible © Digital Integrated Circuits 2 nd Fully flexible -- A flexible design may allow ‘late binding’ , in which the application can still be changed after the chip has gone to fabrication. -- COST is performance or energy efficiency. -- Providing programmability means adding overhead to implementation. Flexibility (or application scope) Design Methodologie
Design Methodology • Design process traverses iteratively between three abstractions: behavior, structure, and geometry • More and more automation for each of these steps © Digital Integrated Circuits 2 nd Design Methodologie
Implementation Choices Digital Circuit Implementation Approaches Custom Semicustom Cell-based Standard Cells Compiled Cells Macro Cells Array-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's) custom: handrcrafted: when performance or design density are important: high cost: long time to market. Only the most performance-critical modules such as the PLLs and clock buffers are designed manually. Library cell design is the only area where custom design still thrives today © Digital Integrated Circuits 2 nd Design Methodologie
The Custom Approach Intel 4004 (handcrafted) © Digital Integrated Circuits 2 nd Courtesy Intel Design Methodologie
Transition to Automation and Regular Structures Intel 4004 (‘ 71) Intel 8080 Intel 8286 © Digital Integrated Circuits 2 nd Intel 8085 Intel 8486 Courtesy Intel Design Methodologie
cells) --Reduce the implementation effort by reusing a limited library of cells. --The constrained nature of library reduces the possibility of fine-tuning the design. --Layout is automatically generated using the cells in the library --In the standard-cell philosophy, cells are placed in rows that are separated by routing channels. --Cell heights shall be identical but the cell width may vary for complex cells --Routing channel requirements are reduced by presence of more interconnect layers --interconnect wire length can be reduced by feedthrough cells © Digital Integrated Circuits 2 nd Design Methodologie
Standard Cell — Example Standard cell design in a three-layer metal technology. Wiring channels represent a substantial amount of the chip area. [Brodersen 92] © Digital Integrated Circuits 2 nd Design Methodologie
Standard Cell – The New Generation --using 7 metal layers --more than 90% density which means that virtually all of the chip area is covered by logic cells --Cell-structure hidden under interconnect layers © Digital Integrated Circuits 2 nd Design Methodologie
Standard Cell - Example all information is provided with the cell 3 -input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time © Digital Integrated Circuits 2 nd Design Methodologie
Automatic Cell Generation Process Initial transistor geometries Placed transistors Routed cell Compacted cell Finished cell Cost of implementing and characterizing a library of cells © Digital Integrated Circuits 2 nd Courtesy Acadabra Design Methodologie
A Historical Perspective: the PLA Product terms x 0 x 1 x 2 AND plane OR plane f 0 x 1 PLA is a regular structured design approach. This methodology enabled the automatic layout generation of two-level logic circuits, in a predictable fashion in terms of area and performance. The emergence of automatic logic synthesis tools for two-level logic made it possible to translate any possible Boolean expression into an optimized two-level (SOP/POS) logic. f 1 x 2 © Digital Integrated Circuits 2 nd Design Methodologie
Two-Level Logic Every logic function can be expressed in sum-of-products format (AND-OR) minterm Inverting format (NORNOR) more effective large fan-in NAND-NAND confign. has slow speed but lower power dissipation © Digital Integrated Circuits 2 nd Design Methodologie
PLA Layout – Exploiting Regularity And-Plane V DD © Digital Integrated Or-Plane f NOR-NOR equation implementation Circuits 2 nd GND Design Methodologie
Cells that contain a complexity that surpasses what is found in typical standard-cell library are called macrocells (hard/soft) Macro. Modules 256 32 (or 8192 bit) SRAM Generated by hard-macro module generator Hard Macro: represents a module with a given functionality and predetermined physical design. The relative location of transistors and wiring within the module is fixed. Advantages: dense layout, optimized and predictable performance and power dissipation, reusability helps to offset the initial design cost. Disadvantages: Hard to port the design to other technologies, © Digital Integrated Circuits 2 nd Design Methodologie
“Soft” Macro. Modules Soft Macro: represents a module with a given functionality, but without a specific physical design. The relative location of transistors and wiring within the module may vary from instance to instance. This means that the timing data can only be determined after the final synthesis and placement and routing steps– in other words, the process is unpredictable. Advantages: well defined timing guarantees, can be ported over a wide range of technologies and processes, minimum design effort and cost over wide set of designs, soft macro generator has all system information and constraints so that it can produce clever structures that are more efficient than what logic synthesis would produce. Disadvantages: Hard to port the design to other technologies, © Digital Integrated Circuits 2 nd Synopsys Design. Compiler Design Methodologie
Two instances of an 8 X 8 multiplier module with different aspect ratios are shown. The contribution of macrocell generator is to translate the compact input description into an optimized connection of standard cells that meets the timing constraints. The “soft” approach has the advantage that modules with different aspect ratios can be easily generated. © Digital Integrated Circuits 2 nd Design Methodologie
Macromodules are aquired from third-party vendors, through license agreements or paying royality. These are called IPs. “Intellectual Property” A Protocol Processor for Wireless © Digital Integrated Circuits 2 nd Design Methodologie
Semicustom Design Flow Design Iteration Design Capture Pre-Layout Simulation Behavioral HDL Logic Synthesis Structural Floorplanning Post-Layout Simulation Placement Circuit Extraction Routing Physical Tape-out © Digital Integrated Circuits 2 nd Design Methodologie
The “Design Closure” Problem Each of these iterations may take several days—just routing a complex chip may take a week on the most advanced computers! The number of needed iterations grow with scaling of technology. This problem called timing closure, made it obvious that new solution and change in design methodology were required Iterative Removal of Timing Violations (white lines) © Digital Integrated Circuits 2 nd Courtesy Synopsys Design Methodologie
Integrating Synthesis with Physical Design RTL (Timing) Constraints Physical Synthesis Macromodules Fixed netlists Netlist with Place-and-Route Info Place-and-Route Optimization © Digital Integrated Circuits 2 nd Artwork Design Methodologie
Late-Binding Implementation Design automation does not address the time spent in manufacturing process. All the design methodologies require a complete run through the fabrication process. This can take from three weeks to several months, and it can substantially delay the introduction of product. A number of alternative approaches have been devised that do not require a complete run through the manufacturing process. This comes at the expense of lower performance , lower integration density, or higher power dissipation. Array-based Pre-diffused (Gate Arrays) or Sea of Gates © Digital Integrated Circuits 2 nd Pre-wired (FPGA's) Design Methodologie
Gate Array — Sea-of-gates Channeled Non-channeled Uncommited Cell Committed Cell (4 -input NOR) © Digital Integrated Circuits 2 nd Design Methodologie
Sea-of-gate Primitive Cells Using oxide-isolation between gates Using gate-isolation Multiple cells are needed when implementing a flip-flop Dog-bone terminations of poly provides denser routing. In Long rows of transistors sharing the same diffusion area, it is necessary to turn off some devices to provide isolation between the neighboring gates by tying NMOS to GND and PMOS to VDD. This technique is called ‘gateisolation’, wastes few transistors to provide isolation but it provides an overall high transistor density. © Digital Integrated Circuits 2 nd Design Methodologie
Example: Base Cell of Gate. Isolated GA The cell is one routing track wide, and contains one n. MOS and one p. MOS. Also shown is a base cell containing all possible contact positions. There is room for 21 contacts in the vertical direction, which means that the cell has a height of 21 tracks. © Digital Integrated Circuits 2 nd From Smith 97 Design Methodologie
Designs with large number of gates have large memory requirements. Some area is set aside for dedicated memory modules (more efficient design). Mixing of gate arrays with fixed macros is called embedded gate-array approach. Other modules such as microprocessors and microcontrollers are also ideal candidates for embedding. Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA 300 K (0. 6 mm CMOS) © Digital Integrated Circuits 2 nd Courtesy LSI Logic Design Methodologie
Prewired Arrays Classification of prewired arrays (or fieldprogrammable devices): q Based on Programming Technique § Fuse-based (program-once) § Non-volatile EPROM based § RAM based q Programmable Logic Style § Array-Based § Look-up Table q Programmable Interconnect Style § Channel-routing § Mesh networks © Can be programmed in the field (i. e. , outside the semiconductor foundry) avoiding dedicated manufacturing steps Digital Integrated Circuits 2 nd Design Methodologie
Fuse-Based FPGA antifuse polysilicon ONO dielectric n+ antifuse diffusion 2 l Open by default, closed by applying program current pulse, dielectric melts and permanent connection is formed © Digital Integrated Circuits 2 nd From Smith 97 Design Methodologie
Array-Based Programmable Logic I 5 I 4 I 3 I 2 I 1 I 0 Programmable OR array Programmable AND array I 3 I 2 I 1 I 0 Programmable OR array Fixed AND array O 3 O 2 O 1 O 0 PLA I 5 I 4 I 3 I 2 I 1 I 0 Fixed OR array Programmable AND array O 3 O 2 O 1 O 0 PROM O 3 O 2 O 1 O 0 PAL Indicates programmable connection Indicates fixed connection © Digital Integrated Circuits 2 nd Design Methodologie
Programming a PROM 1 X 2 X 1 X 0 : programmed node NA NA f 1 f 0 © Digital Integrated Circuits 2 nd Design Methodologie
Look-up Table Based Logic Cell a two bit large memory called lookup table is programmed to capture the truth table of the function. EXOR for example in above figure. The i/p variables serve as control inputs to a multiplexer which picks the appropriate value from the memory. © Digital Integrated Circuits 2 nd Design Methodologie
LUT-Based Logic Cell 4 C 1. . C 4 xx D 4 D 3 D 2 Logic function of G 1 -G 4 D 1 F 2 F 1 Xilinx 4000 Series © Digital Integrated Circuits 2 nd xxxx Bits control xxxx F’ G’ H’ D s Q G’ H’ EC R Logic function of F 1 -F 4 x xxxx Din Logic functionx of H 1 -H 4 F 3 xxxx xx x x Bits control Din F’ G’ H’ xxxx D S Q xx EC R H P x x Multiplexer Controlled by Configuration Program Courtesy Xilinx Design Methodologie
Array-Based Programmable Wiring Interconnect Point Programmed interconnection Input/output pin Cell Horizontal tracks Vertical tracks © Digital Integrated Circuits 2 nd Design Methodologie
Network Switch Box Connect Box Interconnect Point © Digital Integrated Circuits 2 nd. Courtesy Dehon and Wawrzyniek Design Methodologie
Transistor Implementation of Mesh © Digital Integrated Circuits 2 nd. Courtesy Dehon and Wawrzyniek Design Methodologie
Hierarchical Mesh Network Use overlayed mesh to support longer connections Reduced fanout and reduced resistance © Digital Integrated Circuits 2 nd. Courtesy Dehon and Wawrzyniek Design Methodologie
Altera MAX Interconnect Architecture column channel row channel t PIA LAB 1 LAB 2 LAB PIA t PIA LAB 6 Array-based (MAX 3000 -7000) © Digital Integrated Circuits 2 nd Mesh-based (MAX 9000) Courtesy Altera Design Methodologie
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