THE INVERTER DYNAMICS Adapted from Rabaeys Digital Integrated

Inverter Dynamics v Dynamic Behavior v Delay Definitions v Voltage Transfer Characteristic v Switching Threshold v Propagation Delay v Transient Response v Inverter Sizing v Power Dissipation v Short Circuit Currents v Technology Scaling EE 415 VLSI Design

Dynamic Behavior Propagation Delay, Tp • Defines how quickly output is affected by input • Measured between 50% transition from input to output • tp. LH defines delay for output going from low to high • tp. HL defines delay for output going from high to low • Overall delay, tp, defined as the average of tp. LH and tp. HL EE 415 VLSI Design

Dynamic Behavior Rise and fall time, Tr and Tf • Defines slope of the signal • Defined between the 10% and 90% of the signal swing Propagation delay and rise and fall times affected by the fan-out due to larger capacitance loads EE 415 VLSI Design

Delay Definitions EE 415 VLSI Design

The Ring Oscillator • A standard method is needed to measure the gate delay • It is based on the ring oscillator • 2 Ntp >> tf + tr for properation EE 415 VLSI Design

Ring Oscillator EE 415 VLSI Design

Voltage Transfer Characteristic EE 415 VLSI Design

CMOS Inverter Load Characteristics G S D D G S EE 415 VLSI Design

PMOS Load Lines IDn G V in = VDD +VGSp IDn = - IDp V out = VDD +VDSp S D D Vout IDp G Vin=0 S IDn Vin=3 VGSp=-2 VGSp=-5 EE 415 VLSI Design V DSp Vin = VDD+VGSp IDn = - IDp Vin=0 Vin=3 VDSp Vout = V DD+VDSp Vout

CMOS Inverter Load Lines IDn (A) PMOS NMOS X 10 -4 Vin = 0 V Vin = 2. 5 V Vin = 0. 5 V Vin = 2. 0 V Vin = 1 V Vin = 1. 5 V Vin = 0. 5 V Vin = 2 V Vin = 1. 5 V Vin = 1. 0 V Vin = 0. 5 V Vin = 1. 5 V Vin = 2. 0 V Vin = 2. 5 V Vout (V) Vin = 0 V 0. 25 um, W/Ln = 1. 5, W/Lp = 4. 5, VDD = 2. 5 V, VTn = 0. 4 V, VTp = -0. 4 V EE 415 VLSI Design

CMOS Inverter VTC NMOS off PMOS res Vout (V) NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat Vin (V) EE 415 VLSI Design NMOS res PMOS off

Cutoff Linear Saturation p. MOS Vin -VDD= VGS> VT Vin -VDD=VGS< VT Vin -Vout=VGD< VT Vin -VDD=VGS> VT Vin -Vout=VGD>VT n. MOS Vin = VGS< VT Vin =VGS> VT Vin -Vout =VGD> VT Vin =VGS> VT Vin -Vout =VGD< VT Regions of operations For n. MOS and p. MOS In CMOS inverter G S D D G S EE 415 VLSI Design

CMOS Inverter Load Characteristics • For valid dc operating points: • current through NMOS = current through PMOS • => dc operating points are the intersection of load lines • All operating points located at high or low output levels • => VTC has narrow transition zone • high gain of transistors during switching • transistors in saturation • high transconductance (gm) • high output resistance (voltage controlled current source) EE 415 VLSI Design

Switching Threshold l l l VM where Vin = Vout (both PMOS and NMOS in saturation since VDS = VGS) VM r. VDD/(1 + r) where r = kp. VDSATp/kn. VDSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Want VM = VDD/2 (to have comparable high and low noise margins), so want r 1 (W/L)p = kn’VDSATn(VM-VTn-VDSATn/2) (W/L)n kp’VDSATp(VDD-VM+VTp+VDSATp/2) EE 415 VLSI Design

Switch Threshold Example l In 0. 25 m CMOS process, using parameters from table, VDD = 2. 5 V, and minimum size NMOS ((W/L)n of 1. 5) VT 0(V) (V 0. 5) VDSAT(V) k’(A/V 2) (V-1) NMOS 0. 43 0. 4 0. 63 115 x 10 -6 0. 06 PMOS -0. 4 -1 -30 x 10 -6 -0. 1 (W/L)p 115 x 10 -6 0. 63 (1. 25 – 0. 43 – 0. 63/2) (W/L)n = -30 x x 10 -6 -1. 0 x (1. 25 – 0. 4 – 1. 0/2) (W/L)p = 3. 5 x 1. 5 = 5. 25 for a VM of 1. 25 V EE 415 VLSI Design = 3. 5

Simulated Inverter VM VM is relatively insensitive to variations in device ratio l setting the ratio to 3, 2. 5 and 2 gives VM’s of 1. 22 V, 1. 18 V, and 1. 13 V VM (V) q Increasing the width of the PMOS moves VM towards VDD q ~3. 4 . 1 (W/L)p/(W/L)n Note: x-axis is semilog EE 415 VLSI Design

Noise Margins Determining VIH and VIL By definition, VIH and VIL are where d. Vout/d. Vin = -1 (= gain) Vout VOH = VDD VM VOL = GND Vin A piece-wise linear approximation of VTC EE 415 VLSI Design NMH = VDD - VIH NML = VIL - GND Approximating: VIH = VM - VM /g VIL = VM + (VDD - VM )/g So high gain in the transition region is very desirable

CMOS Inverter VTC from Simulation 0. 25 um, (W/L)p/(W/L)n = 3. 4 (W/L)n = 1. 5 (min size) VDD = 2. 5 V Vout (V) VM 1. 25 V, g = -27. 5 VIL = 1. 2 V, VIH = 1. 3 V NML = NMH = 1. 2 (actual values are VIL = 1. 03 V, VIH = 1. 45 V NML = 1. 03 V & NMH = 1. 05 V) Vin (V) EE 415 VLSI Design Output resistance low-output = 2. 4 k high-output = 3. 3 k

Gain Determinates Vin Gain is a function of the current slope in the saturation region, for Vin = VM gain (1+r) g -----------------(VM-VTn-VDSATn/2)( n - p ) üDetermined by technology parameters, especially . üOnly designer influence through supply voltage and VM (transistor sizing). EE 415 VLSI Design

Impact of Process Variation Vout (V) Good PMOS Bad NMOS Nominal Bad PMOS Good NMOS Vin (V) l. Pprocess variations (mostly) cause a shift in the switching threshold EE 415 VLSI Design

Vout (V) Scaling the Supply Voltage Gain=-1 Vin (V) Device threshold voltages are kept (virtually) constant EE 415 VLSI Design Vin (V) Device threshold voltages are kept (virtually) constant

Propagation Delay EE 415 VLSI Design

Switch Model of Dynamic Behavior VDD Rp Vout CL Rn CL Vin = V DD Vin = 0 l Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn) EE 415 VLSI Design

What is the Inverter Driving? VDD M 2 Vin Cg 4 Cdb 2 Cgd 12 M 4 Vout M 1 Cdb 1 Cw Vout 2 Cg 3 M 3 Interconnect Fanout Simplified Model EE 415 VLSI Design Vin Vout CL

CMOS Inverter Propagation Delay Approach 1 EE 415 VLSI Design

CMOS Inverter Propagation Delay Approach 2 EE 415 VLSI Design

CMOS Inverter: Transient Response How can the designer build a fast gate? • tp. HL = f(Ron*CL) • Keep output capacitance, CL, small • low fan-out • keep interconnections short (floor-plan your layout!) • Decrease on-resistance of transistor • increase W/L ratio • make good contacts (slight effect) EE 415 VLSI Design

MOS Transistor Small Signal Model Define EE 415 VLSI Design

Determining VIH and VIL are based on derivative of VTC equal to -1 EE 415 VLSI Design

Transient Response ? tp = 0. 69 CL (Reqn+Reqp)/2 tp. HL EE 415 VLSI Design tp. LH

Inverter Transient Response VDD=2. 5 V 0. 25 m W/Ln = 1. 5 W/Lp = 4. 5 Reqn= 13 k ( 1. 5) Reqp= 31 k ( 4. 5) Vout (V) Vin tp. HL tf tp. LH tr tp. HL = 36 psec tp. LH = 29 psec so t (sec) x 10 -10 From simulation: tp. HL = 39. 9 psec and EE 415 VLSI Design tp = 32. 5 psec tp. LH = 31. 7 psec

Delay as a function of VDD EE 415 VLSI Design

Sizing Impacts on Delay x 10 -11 for a fixed load The majority of improvement is obtained for S = 5. tp(sec) Sizing factors larger than 10 barely yields any extra gain (and cost significantly more area). S EE 415 VLSI Design self-loading effect (intrinsic capacitance dominates)

PMOS/NMOS Ratio Effects x 10 -11 tp(sec) tp. LH EE 415 VLSI Design tp. HL tp = (W/Lp)/(W/Ln) of 2. 4 (= 31 k /13 k ) gives symmetrical response of 1. 6 to 1. 9 gives optimal performance

Input Signal Rise/Fall Time x 10 -11 l tp(sec) l The input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging CL and impacts propagation delay. l l tp increases linearly with increasing input rise time, tr, once tr > tp tr is due to the limited driving capability of the preceding gate EE 415 VLSI Design ts(sec) for a minimum-size inverter with a fan-out of a single gate x 10 -11

Inverter Sizing EE 415 VLSI Design

CMOS Inverter Sizing Out metal 1 metal 2 pdiff metal 1 -diff via In metal 1 -poly via polysilicon VDD PMOS (4/. 24 = 16/1) NMOS (2/. 24 = 8/1) ndiff GND EE 415 VLSI Design metal 2 -metal 1 via

Inverter Delay • Minimum length devices, L=0. 25 m • Assume that for WP = 2 WN =2 W • same pull-up and pull-down currents • approx. equal resistances RN = RP • approx. equal rise tp. LH and fall tp. HL delays • Analyze as an RC network Delay (D): tp. HL = (ln 2) RNCL Load for the next stage: EE 415 VLSI Design tp. LH = (ln 2) RPCL 2 W W

Inverter with Load Delay RW CL RW Load (CL) t p = k R WC L k is a constant, equal to 0. 69 Assumptions: no load -> zero delay EE 415 VLSI Design Wunit = 1

Inverter with Load CP = 2 Cunit Delay 2 W W Cint CL CN = Cunit Delay = k. RW(Cint + CL) = k. RW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load) EE 415 VLSI Design Load

Delay Formula t p = k. R W C int (1 + C L / C int ) = t p 0 (1 + f / g Cint = g. Cgin with g 1 f = CL/Cgin effective fanout R = Runit/W ; tp 0 = 0. 69 Runit. Cunit EE 415 VLSI Design Cint =WCunit )

Inverter Chain l Real goal is to minimize the delay through an inverter chain In Out Cg, 1 1 2 N CL the delay of the j-th inverter stage is tp, j = tp 0 (1 + Cg, j+1/( Cg, j)) = tp 0(1 + fj/ ) and tp = tp 1 + tp 2 +. . . + tp. N so l tp = tp, j = tp 0 (1 + Cg, j+1/( Cg, j)) If CL is given » How should the inverters be sized? » How many stages are needed to minimize the delay? EE 415 VLSI Design

Optimum Delay and Number of Stages When each stage is sized by f and has same fanout f: Effective fanout of each stage: Minimum path delay EE 415 VLSI Design

Example In C 1 Out 1 f f 2 C L= 8 C 1 CL/C 1 has to be evenly distributed across N = 3 stages: Notice that in this case we may not have any time savings EE 415 VLSI Design

Optimal Number of Inverters l l l What is the optimal value for N given F (=f. N) ? » if the number of stages is too large, the intrinsic delay dominates » if the number of stages is too small, the effective fanout dominates The optimum N is found by differentiating the minimum delay divided by the number of stages and setting the result to 0, For = 0 (ignoring self-loading) N = ln (F) and the effective-fan out becomes f = e = 2. 71828 EE 415 VLSI Design

Optimum Number of Stages For a given load, CL and given input capacitance Cin Find optimal sizing f For g = 0, f = e, N = ln. F EE 415 VLSI Design

normalized delay t Fop Optimum Effective Fan-Out l f Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area). » Common practice to use f = 4 (for = 1) » Too many stages has a negative impact on delay EE 415 VLSI Design

Example of Inverter (Buffer) Staging 1 Cg, 1 = 1 CL = 64 Cg, 1 8 1 Cg, 1 = 1 CL = 64 Cg, 1 4 1 16 Cg, 1 = 1 1 2. 8 Cg, 1 = 1 EE 415 VLSI Design CL = 64 Cg, 1 8 22. 6 CL = 64 Cg, 1 N f tp 1 64 65 2 8 18 3 4 15 4 2. 8 15. 3

Impact of Buffer Staging for Large CL l F ( = 1) Unbuffered Two Stage Chain Opt. Inverter Chain 10 11 8. 3 100 101 22 16. 5 1, 000 1001 65 24. 8 10, 000 10, 001 202 33. 1 Impressive speed-ups with optimized cascaded inverter chain for very large capacitive loads. EE 415 VLSI Design

Design Challenge l Keep signal rise times < gate propagation delays. » good for performance » good for power consumption l Keeping rise and fall times of the signals of approximately equal values is one of the major challenges in - slope engineering. EE 415 VLSI Design

Power Dissipation EE 415 VLSI Design

Power Dissipation • Power consumption determines heat dissipation and energy consumption • Power influences design decisions: • packaging and cooling • width of supply lines • power-supply capacity • # of transistors integrated on a single chip Power requirements make high density bipolar ICs impossible (feasibility, cost, reliability) EE 415 VLSI Design

Power Dissipation Supply-line sizing Battery drain, cooling EE 415 VLSI Design

Power Dissipation • Ppeak = static power + dynamic power • Dynamic power: • (dis)charging capacitors • temporary paths from VDD to VSS • proportional to switching frequency • Static power: • static conductive paths between rails • leakage • increases with temperature EE 415 VLSI Design

Power Dissipation • Propagation delay is related to power consumption • tp determined by speed of charge transfer • fast charge transfer => fast gate • fast gate => more power consumption • Power-delay product (PDP) • quality measure for switching device • PDP = energy consumed /gate / switching event • measured using ring oscillator EE 415 VLSI Design

Power Dissipation Supply-line sizing Energy consumed /gate /switching event Battery drain, cooling EE 415 VLSI Design

CMOS Inverter: Steady State Response • CMOS technology: • No path exists between VDD and VSS in steady state • No static power consumption! (ideally) • Main reason why CMOS replaced NMOS • NMOS technology: • Has NMOS pull-up device that is always ON • Creates voltage divider when pull-down is ON • Power consumption limits # devices / chip EE 415 VLSI Design

Dynamic Power Dissipation Vdd Vin Vout CL Energy/transition = CL * Vdd 2 Power = Energy/transition * f = CL * Vdd 2 * f Not a function of transistor sizes! Need to reduce CL, Vdd, and f to reduce power. EE 415 VLSI Design

Modification for Circuits with Reduced Swing EE 415 VLSI Design

Node Transition Activity and Power EE 415 VLSI Design

Short Circuit Currents EE 415 VLSI Design

How to keep Short-Circuit Currents Low? Short circuit current goes to zero if tout_fall >> tin_rise, but can’t do this for cascade logic. EE 415 VLSI Design

Minimizing Short-Circuit Power Vdd =3. 3 Vdd =2. 5 Vdd =1. 5 Keep the input and output rise/fall times equal If VDD<Vth+|Vtp| then short circuit power can be eliminated EE 415 VLSI Design

Leakage Sub-threshold currents rise exponentially with temperature. EE 415 VLSI Design

Reverse-Biased Diode Leakage JS = 10 -100 p. A/mm 2 at 25 deg C for 0. 25 mm CMOS JS doubles for every 9 deg C! EE 415 VLSI Design

Subthreshold Leakage Component EE 415 VLSI Design

Static Power Consumption EE 415 VLSI Design

Principles for Power Reduction l Prime choice: Reduce voltage! » Supply voltage was reduced from 5 V to 1 V over the years » 25 time reduction of switching power l l Reduce switching activity Reduce physical capacitance » Device Sizing: for F=20 – fopt(energy)=3. 53, fopt(performance)=4. 47 EE 415 VLSI Design

Bad News l Voltage scaling has stopped as well » k. T/q does not scale » Vth scaling has power consequences l If Vdd does not scale » Energy scales slowly EE 415 VLSI Design Ed Nowak, IBM

Impact of Technology Scaling EE 415 VLSI Design

Goals of Technology Scaling l Make things cheaper: » Want to sell more functions (transistors) per chip for the same money » Build same products cheaper, sell the same part for less money » Price of a transistor has to be reduced l But also want to be faster, smaller, lower power EE 415 VLSI Design

Technology Scaling l Goals of scaling the dimensions by 30%: » Reduce gate delay by 30% (increase operating frequency by 43%) » Double transistor density » Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency l l Die size used to increase by 14% per generation Technology generation spans 2 -3 years EE 415 VLSI Design

Technology Nodes Green – in use Orange - in development Blue –in plans EE 415 VLSI Design

Minimum Feature Size (nm) Technology Nodes 350 180 100 50 25 13 http: //broadband 02. ici. ro/program/klingenstein_3 d. pdf EE 415 VLSI Design

Minimum Feature Size (nm) Technology Nodes and Minimum Feature Sizes 350 250 180 130 90 65 45 32 22 15 10 EE 415 VLSI Design http: //broadband 02. ici. ro/program/klingenstein_3 d. pdf

Leakage currents Currents [A/ m] http: //broadband 02. ici. ro/program/klingenstein_3 d. pdf EE 415 VLSI Design

Supply voltage http: //broadband 02. ici. ro/program/klingenstein_3 d. pdf EE 415 VLSI Design

ITRS Technology Roadmap Acceleration Continues EE 415 VLSI Design

ITRS Technology Roadmap Acceleration Continues SAT TV/WLAN IMT 2000 UWC 136 Satellite Comm. LMDS RADAR Automotive Military 76. . . 78 94 2016 2013 2010 2007 2004 2001 http: //broadband 02. ici. ro/program/klingenstein_3 d. pdf 1999 CMOS EE 415 VLSI Design Si. Ge-BICMOS III-V (In. P)