CSE 477 VLSI Digital Circuits Fall 2003 Lecture

CSE 477 VLSI Digital Circuits Fall 2003 Lecture 12&13: Designing for Low Power Mary Jane Irwin ( www. cse. psu. edu/~mji ) www. cse. psu. edu/~cg 477 [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, © 2003 Rabaey, A. Chandrakasan, B. Nikolic] CSE 477 L 12&13 Low Power. 1 J. Irwin&Vijay, PSU, 2003

Review: Designing Fast CMOS Gates q Transistor sizing q Progressive transistor sizing l q Transistor ordering l q fet closest to the output is smallest of series fets put latest arriving signal closest to the output Logic structure reordering l replace large fan-in gates with smaller fan-in gate network q Logical effort q Buffer (inverter) insertion l l separate large fan-in from large CL with buffers uses buffers so there are no more than four TGs in series CSE 477 L 12&13 Low Power. 2 Irwin&Vijay, PSU, 2003

Why Power Matters q Packaging costs q Power supply rail design q Chip and system cooling costs q Noise immunity and system reliability q Battery life (in portable systems) q Environmental concerns l l Office equipment accounted for 5% of total US commercial energy usage in 1993 Energy Star compliant systems CSE 477 L 12&13 Low Power. 3 Irwin&Vijay, PSU, 2003

Why worry about power? – Power Dissipation Lead microprocessors power continues to increase Power (Watts) 100 P 6 Pentium ® 10 8086 286 1 8008 4004 486 386 8085 8080 0. 1 1974 1978 1985 1992 2000 Year Power delivery and dissipation will be prohibitive Source: Borkar, De Intel CSE 477 L 12&13 Low Power. 4 Irwin&Vijay, PSU, 2003

Why worry about power? – Chip Power Density Sun’s Surface Power Density (W/cm 2) 10000 Rocket Nozzle 1000 …chips might become hot… Nuclear Reactor 100 8086 Hot Plate 10 4004 P 6 8008 8085 Pentium® 386 286 486 8080 1 1970 1980 1990 Year 2000 2010 Source: Borkar, De Intel CSE 477 L 12&13 Low Power. 5 Irwin&Vijay, PSU, 2003

Chip Power Density Distribution Power Map q On-Die Temperature Power density is not uniformly distributed; max junction temperature is determined by hot-spots l l l Silicon is not a good heat conductor Impacts packaging, w. r. t. cooling and packaging costs Impacts reliability – lifetime reduces by half for every 10ºC increase in temperature CSE 477 L 12&13 Low Power. 6 Irwin&Vijay, PSU, 2003

Problem Illustration CSE 477 L 12&13 Low Power. 7 Irwin&Vijay, PSU, 2003

Why worry about power? – Machine Room Design “Most data centers today cannot support the power and cooling requirements of a large number of new systems. ” Roger Schmidt, IBM q Most data centers have a capacity of 40 to 70 W/ft 2 l q They will need to support 500 W/ft 2 in the next few years Large servers l IBM z 900 (single rack) – 9. 2 k. W l IBM p 690 (single rack) – 12. 5 k. W l IBM p 655 – 28 k. W (1915 W/ft 2) CSE 477 L 12&13 Low Power. 8 Irwin&Vijay, PSU, 2003

Machine Room Cooling Implications q If the trend continues a 200, 000 ft 2 center could require 100 Megawatts of power l Add 60 MW for mechanical room support l 160 MW is 16% of the output of a typical nuclear power plant l Yearly electricity costs would exceed $100 M Also cooling water resource and waste issues l CSE 477 L 12&13 Low Power. 9 Floor load size 36 sq ft Physical size 14. 5 sq ft Service size 25 sq ft Cooling size 190 sq ft (8% floor utilization) Source: E. Kronstadt, IBM Irwin&Vijay, PSU, 2003

Why worry about power? – The Environment EPA estimates that 10% of electricity generated is consumed by desktop computers Dedicated nuclear reactors for data centers? ? CSE 477 L 12&13 Low Power. 10 Irwin&Vijay, PSU, 2003

Why worry about power ? – Battery Size/Weight 50 Battery (40+ lbs) Nominal Capacity (W-hr/lb) Rechargable Lithium 40 Ni-Metal Hydride 30 20 Nickel-Cadmium 10 0 65 70 75 80 85 90 95 Year Expected battery lifetime increase over the next 5 years: 30 to 40% CSE 477 L 12&13 Low Power. 11 From Rabaey, 1995 Irwin&Vijay, PSU, 2003

Why worry about power? – Standby Power q Year 2002 2005 2008 2011 2014 Power supply Vdd (V) Threshold VT (V) 1. 5 0. 4 1. 2 0. 4 0. 9 0. 35 0. 7 0. 3 0. 6 0. 25 Drain leakage will increase as VT decreases to maintain noise margins and meet frequency demands, leading to excessive battery draining standby power consumption. 8 KW 50% …and phones leaky! 1. 7 KW Standby Power 40% 30% 20% 400 W 88 W 12 W 10% 0% 2000 CSE 477 L 12&13 Low Power. 12 2004 2006 2008 Source: Borkar, De Intel Irwin&Vijay, PSU, 2003

Power and Energy Figures of Merit q Power consumption in Watts l q q Peak power l determines power ground wiring designs l sets packaging limits l impacts signal noise margin and reliability analysis Energy efficiency in Joules l q determines battery life in hours rate at which power is consumed over time Energy = power * delay l l Joules = Watts * seconds lower energy number means less power to perform a computation at the same frequency CSE 477 L 12&13 Low Power. 13 Irwin&Vijay, PSU, 2003

Power versus Energy Power is height of curve Watts Lower power design could simply be slower Approach 1 Approach 2 Watts time Energy is area under curve Two approaches require the same energy Approach 1 Approach 2 time CSE 477 L 12&13 Low Power. 14 Irwin&Vijay, PSU, 2003

PDP and EDP q Power-delay product (PDP) = Pav * tp = (CLVDD 2)/2 l l q PDP is the average energy consumed per switching event (Watts * sec = Joule) lower power design could simply be a slower design Energy-delay product (EDP) = PDP * tp = Pav * tp 2 l EDP is the average energy consumed multiplied by the computation time required l takes into account that one can trade increased delay for lower energy/operation (e. g. , via supply voltage scaling that increases delay, but decreases energy consumption) l energy-delay energy delay allows one to understand tradeoffs better CSE 477 L 12&13 Low Power. 15 Irwin&Vijay, PSU, 2003

Understanding Tradeoffs Which design is the “best” (fastest, coolest, both) ? Lower EDP b Energy better q c a d 1/Delay better CSE 477 L 12&13 Low Power. 17 Irwin&Vijay, PSU, 2003

CMOS Energy & Power Equations E = CL VDD 2 P 0 1 + tsc VDD Ipeak P 0/1 1/0 + VDD Ileak f = P * fclock P = CL VDD 2 f Dynamic power CSE 477 L 12&13 Low Power. 18 + tsc. VDD Ipeak f Short-circuit power + VDD Ileak Leakage power Irwin&Vijay, PSU, 2003

Dynamic Power Consumption Vdd Vin Vout CL f 0 1 Energy/transition = CL * VDD * P 0 1 2 Pdyn = Energy/transition * f = CL * VDD 2 * P 0 1 * f Pdyn = CEFF * VDD 2 * f where CEFF = P 0 1 CL Not a function of transistor sizes! Data dependent - a function of switching activity! CSE 477 L 12&13 Low Power. 19 Irwin&Vijay, PSU, 2003

Lowering Dynamic Power Capacitance: Function of fan-out, wire length, transistor sizes Supply voltage: Has been dropping with successive generations Pdyn = CL VDD 2 P 0 1 f Activity factor: How often, on average, do wires switch? CSE 477 L 12&13 Low Power. 21 Clock frequency: Increasing… Irwin&Vijay, PSU, 2003

Short Circuit Power Consumption Vin Isc Vout CL Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting. CSE 477 L 12&13 Low Power. 22 Irwin&Vijay, PSU, 2003

Short Circuit Currents Determinates Esc = tsc VDD Ipeak P 0 1 Psc = tsc VDD Ipeak f 0 1 q Duration and slope of the input signal, tsc q Ipeak determined by l the saturation current of the P and N transistors which depend on their sizes, process technology, temperature, etc. l strong function of the ratio between input and output slopes - a function of CL CSE 477 L 12&13 Low Power. 23 Irwin&Vijay, PSU, 2003

Impact of CL on Psc Isc 0 Vin Isc Imax Vout CL Vin Vout CL Large capacitive load Small capacitive load Output fall time significantly larger than input rise time. Output fall time substantially smaller than the input rise time. CSE 477 L 12&13 Low Power. 24 Irwin&Vijay, PSU, 2003

Ipeak as a Function of CL x 10 -4 When load capacitance is small, Ipeak is large. Ipeak (A) CL = 20 f. F CL = 100 f. F CL = 500 f. F x 10 -10 time (sec) Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals slope engineering. 500 psec input slope CSE 477 L 12&13 Low Power. 25 Irwin&Vijay, PSU, 2003

Psc as a Function of Rise/Fall Times When load capacitance is small (tsin/tsout > 2 for VDD > 2 V) the power is dominated by Psc P normalized VDD= 3. 3 V VDD = 2. 5 V VDD = 1. 5 V If VDD < VTn + |VTp| then Psc is eliminated since both devices are never on at the same time. tsin/tsout W/Lp = 1. 125 m/0. 25 m W/Ln = 0. 375 m/0. 25 m CL = 30 f. F CSE 477 L 12&13 Low Power. 26 normalized wrt zero input rise-time dissipation Irwin&Vijay, PSU, 2003

Leakage (Static) Power Consumption VDD Ileakage Vout Drain junction leakage Gate leakage Subthreshold current Sub-threshold current is the dominant factor. All increase exponentially with temperature! CSE 477 L 12&13 Low Power. 27 Irwin&Vijay, PSU, 2003

Leakage Current Mechanisms I 7 I 8 Polysilicon Gate Source Drain n+ I I I 2 3 6 I 5 I 4 p substrate Bulk (Body) CSE 477 L 12&13 Low Power. 28 Gate oxide n+ I 1 p-n junction reverse bias current (drain junction) I 2 weak inversion (subthreshold current) I 3 DIBL I 4 GIDL I 5 punchthrough I 6 narrow width effect I 7 gate oxide tunneling (gate leakage) I 8 hot carrier injection Irwin&Vijay, PSU, 2003

Leakage as a Function of VT q Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthreshold conduction a dominate component of power dissipation. 10 -2 10 -7 q An 90 m. V/decade VT roll-off - so each 255 m. V increase in VT gives 3 orders of magnitude reduction in leakage (but adversely affects performance) 10 -12 CSE 477 L 12&13 Low Power. 29 Irwin&Vijay, PSU, 2003

TSMC Processes Leakage and VT CL 018 G CL 018 LP CL 018 ULP CL 018 HS CL 015 HS CL 013 HS Vdd 1. 8 V 2 V 1. 5 V 1. 2 V Tox (effective) 42 Å 29 Å 24 Å Lgate 0. 16 m 0. 18 m 0. 13 m 0. 11 m 0. 08 m IDSat (n/p) ( A/ m) 600/260 500/180 320/130 780/360 860/370 920/400 20 1. 60 0. 15 300 1, 800 13, 000 0. 42 V 0. 63 V 0. 73 V 0. 40 V 0. 29 V 0. 25 V 30 22 14 43 52 80 Ioff (leakage) ( A/ m) VTn FET Perf. (GHz) From MPR, 2000 CSE 477 L 12&13 Low Power. 30 Irwin&Vijay, PSU, 2003

Ileakage(n. A/ m) Exponential Increase in Leakage Currents Temp(C) From De, 1999 CSE 477 L 12&13 Low Power. 31 Irwin&Vijay, PSU, 2003

CMOS Energy & Power Equations E = CL VDD 2 P 0 1 + tsc VDD Ipeak P 0/1 1/0 + VDD Ileak f = P * fclock P = CL VDD 2 f Dynamic power (~90% today and decreasing relatively) CSE 477 L 12&13 Low Power. 32 + tsc. VDD Ipeak f Short-circuit power (~8% today and decreasing absolutely) + VDD Ileak Leakage power (~2% today and increasing) Irwin&Vijay, PSU, 2003

Power and Energy Design Space Constant Throughput/Latency Energy Design Time Variable Throughput/Latency Non-active Modules Logic design Active Reduced Vdd (Dynamic) TSizing DFS, DVS Clock Gating Multi-Vdd Leakage (Standby) Multi-VT Stack effect Pin ordering CSE 477 L 12&13 Low Power. 33 Run Time (Dynamic Freq, Voltage Scaling) Sleep Transistors Multi-Vdd Variable VT Input control Irwin&Vijay, PSU, 2003

Dynamic Power as a Function of Device Size Device sizing affects dynamic energy consumption l q The optimal gate sizing factor (f) for dynamic energy is smaller than the one for performance, especially for large F’s l q gain is largest for networks with large overall effective fan-outs (F = CL/Cg, 1) e. g. , for F=20, fopt(energy) = 3. 53 while fopt(performance) = 4. 47 If energy is a concern avoid oversizing beyond the optimal 1. 5 F=1 normalized energy q F=2 1 F=5 0. 5 F=10 F=20 0 1 2 3 4 f 5 6 7 From Nikolic, UCB CSE 477 L 12&13 Low Power. 34 Irwin&Vijay, PSU, 2003

Dynamic Power Consumption is Data Dependent q Switching activity, P 0 1, has two components l l A static component – function of the logic topology A dynamic component – function of the timing behavior (glitching) 2 -input NOR Gate A B Out 0 0 1 0 1 0 0 1 1 0 CSE 477 L 12&13 Low Power. 35 Static transition probability P 0 1 = Pout=0 x Pout=1 = P 0 x (1 -P 0) With input signal probabilities PA=1 = 1/2 PB=1 = 1/2 NOR static transition probability = 3/4 x 1/4 = 3/16 Irwin&Vijay, PSU, 2003

NOR Gate Transition Probabilities q Switching activity is a strong function of the input signal statistics l PA and PB are the probabilities that inputs A and B are one A B 0 A B CL PA 1 0 PB 1 P 0 1 = P 0 x P 1 = (1 -(1 -PA)(1 -PB)) (1 -PA)(1 -PB) CSE 477 L 12&13 Low Power. 36 Irwin&Vijay, PSU, 2003

Transition Probabilities for Some Basic Gates NOR OR NAND XOR P 0 1 = Pout=0 x Pout=1 (1 - PA)(1 - PB)) x (1 - PA)(1 - PB)) PAPB x (1 - PAPB) x PAPB (1 - (PA + PB- 2 PAPB)) x (PA + PB- 2 PAPB) 0. 5 A 0. 5 B X Z For X: P 0 1 = P 0 x P 1 = (1 -PA) PA = 0. 5 x 0. 5 = 0. 25 For Z: P 0 1 = P 0 x P 1 = (1 -PXPB) PXPB = (1 – (0. 5 x 0. 5)) x (0. 5 x 0. 5) = 3/16 CSE 477 L 12&13 Low Power. 38 Irwin&Vijay, PSU, 2003

Inter-signal Correlations q Determining switching activity is complicated by the fact that signals exhibit correlation in space and time l reconvergent fan-out (1 -0. 5)x(1 -(1 -0. 5)) = 3/16 0. 5 A 0. 5 B X Z Reconvergent (1 - 3/16 x 0. 5) x (3/16 x 0. 5) = 0. 085 P(Z=1) = P(B=1) & P(A=1 | B=1) q Have to use conditional probabilities CSE 477 L 12&13 Low Power. 39 Irwin&Vijay, PSU, 2003

Logic Restructuring q Logic restructuring: changing the topology of a logic network to reduce transitions AND: P 0 1 = P 0 x P 1 = (1 - PAPB) x PAPB 0. 5 A B 0. 5 (1 -0. 25)*0. 25 = 3/16 W 7/64 X 15/256 C F 0. 5 D 0. 5 A 0. 5 B 3/16 Y 15/256 F 0. 5 C 0. 5 D Z 3/16 Chain implementation has a lower overall switching activity than the tree implementation for random inputs Ignores glitching effects CSE 477 L 12&13 Low Power. 40 Irwin&Vijay, PSU, 2003

Input Ordering (1 -0. 5 x 0. 2)x(0. 5 x 0. 2)=0. 09 0. 5 A B 0. 2 X C 0. 1 F 0. 2 B C 0. 1 (1 -0. 2 x 0. 1)x(0. 2 x 0. 1)=0. 0196 X A 0. 5 F Which is better wrt transition probabilities? Beneficial to postpone the introduction of signals with a high transition rate (signals with signal probability close to 0. 5) CSE 477 L 12&13 Low Power. 42 Irwin&Vijay, PSU, 2003

Glitching in Static CMOS Networks q Gates have a nonzero propagation delay resulting in spurious transitions or glitches (dynamic hazards) l glitch: node exhibits multiple transitions in a single cycle before settling to the correct logic value A B X Z C ABC 101 000 X Z Unit Delay CSE 477 L 12&13 Low Power. 44 Irwin&Vijay, PSU, 2003

Glitching in an RCA Cin S 15 S 14 S 1 S 2 S 0 S 3 S 4 Cin S 2 S 15 S 10 S 0 CSE 477 L 12&13 Low Power. 45 Irwin&Vijay, PSU, 2003

Balanced Delay Paths to Reduce Glitching q Glitching is due to a mismatch in the path lengths in the logic network; if all input signals of a gate change simultaneously, no glitching occurs 0 0 F 1 0 0 1 F 1 1 F 2 2 F 3 0 0 F 3 F 2 1 So equalize the lengths of timing paths through logic CSE 477 L 12&13 Low Power. 46 Irwin&Vijay, PSU, 2003

Power and Energy Design Space Constant Throughput/Latency Energy Design Time Variable Throughput/Latency Non-active Modules Logic design Active Reduced Vdd (Dynamic) TSizing DFS, DVS Clock Gating Multi-Vdd Leakage (Standby) Multi-VT Stack effect Pin ordering CSE 477 L 12&13 Low Power. 47 Run Time (Dynamic Freq, Voltage Scaling) Sleep Transistors Multi-Vdd Variable VT Input control Irwin&Vijay, PSU, 2003

q Decreasing the VDD decreases dynamic energy consumption (quadratically) q But, increases gate delay (decreases performance) tp(normalized) Dynamic Power as a Function of VDD (V) q Determine the critical path(s) at design time and use high VDD for the transistors on those paths for speed. Use a lower VDD on the other gates, especially those that drive large capacitances (as this yields the largest energy benefits). CSE 477 L 12&13 Low Power. 48 Irwin&Vijay, PSU, 2003

Multiple VDD Considerations q How many VDD? – Two is becoming common l q Many chips already have two supplies (one for core and one for I/O) When combining multiple supplies, level converters are required whenever a module at the lower supply drives a gate at the higher supply (step-up) l If a gate supplied with VDDL drives a gate at VDDH, the PMOS never turns off V - The cross-coupled PMOS transistors do the level conversion - The NMOS transistor operate on a reduced supply l l Vin DDH VDDL Vout Level converters are not needed for a step-down change in voltage Overhead of level converters can be mitigated by doing conversions at register boundaries and embedding the level conversion inside the flipflop (see Figure 11. 47) CSE 477 L 12&13 Low Power. 49 Irwin&Vijay, PSU, 2003

Dual-Supply Inside a Logic Block q Minimum energy consumption is achieved if all logic paths are critical (have the same delay) q Clustered voltage-scaling l Each path starts with VDDH and switches to VDDL (gray logic gates) when delay slack is available l Level conversion is done in the flipflops at the end of the paths CSE 477 L 12&13 Low Power. 51 Irwin&Vijay, PSU, 2003

Power and Energy Design Space Constant Throughput/Latency Energy Design Time Variable Throughput/Latency Non-active Modules Logic design Active Reduced Vdd (Dynamic) TSizing DFS, DVS Clock Gating Multi-Vdd Leakage (Standby) Multi-VT Stack effect Pin ordering CSE 477 L 12&13 Low Power. 52 Run Time (Dynamic Freq, Voltage Scaling) Sleep Transistors Multi-Vdd Variable VT Input control Irwin&Vijay, PSU, 2003

Stack Effect q Subthreshold leakage is a function of the circuit topology and the value of the inputs VT = VT 0 + ( |-2 F + VSB| - |-2 F|) where VT 0 is the threshold voltage at VSB = 0; VSB is the sourcebulk (substrate) voltage; is the body-effect coefficient A A 0 0 1 1 B Out A VX B CSE 477 L 12&13 Low Power. 53 B 0 1 VX VT ln(1+n) 0 VDD-VT 0 ISUB VGS=VBS= -VX VGS=VBS=0 VSG=VSB=0 q Leakage is least when A = B = 0 q Leakage reduction due to stacked transistors is called the stack effect Irwin&Vijay, PSU, 2003

Short Channel Factors and Stack Effect q q In short-channel devices, the subthreshold leakage current depends on VGS, VBS and VDS. The VT of a short -channel device decreases with increasing VDS due to DIBL (drain-induced barrier loading). l Typical values for DIBL are 20 to 150 m. V change in VT per voltage change in VDS so the stack effect is even more significant for short-channel devices. l VX reduces the drain-source voltage of the top nfet, increasing its VT and lowering its leakage even more For our 0. 25 micron technology, VX settles to ~100 m. V in steady state so VBS = -100 m. V and VDS = VDD -100 m. V which is 20 times smaller than the leakage of a device with VBS = 0 m. V and VDS = VDD CSE 477 L 12&13 Low Power. 54 Irwin&Vijay, PSU, 2003

Leakage as a Function of Design Time VT q Reducing the VT increases the subthreshold leakage current (exponentially) l 90 m. V reduction in VT increases leakage by an order of magnitude q But, reducing VT decreases gate delay (increases performance) q Determine the critical path(s) at design time and use low VT devices on the transistors on those paths for speed. Use a high VT on the other logic for leakage control. l A careful assignment of VT’s can reduce the leakage by as much as 80% CSE 477 L 12&13 Low Power. 55 Irwin&Vijay, PSU, 2003

Dual-Thresholds Inside a Logic Block q Minimum energy consumption is achieved if all logic paths are critical (have the same delay) q Use lower threshold on timing-critical paths l Assignment can be done on a per gate or transistor basis; no clustering of the logic is needed l No level converters are needed CSE 477 L 12&13 Low Power. 56 Irwin&Vijay, PSU, 2003

Next Lecture and Reminders q Next lecture (after midterm) l Dynamic logic - Reading assignment – Rabaey, et al, 6. 3 q Reminders l HW#3 due October 16 th (next class) l Project prototypes due on-line by 5: 00 pm on Oct 30 th l HW#4 due November 11 th (not Nov 4 th as on outline) l HW#5 will be optional (due November 20 th) Evening midterm exam scheduled l - Monday, October 20 th , 20: 15 to 22: 15, 62 Willard - Only one midterm conflict scheduled CSE 477 L 12&13 Low Power. 57 Irwin&Vijay, PSU, 2003