CSE 477 VLSI Digital Circuits Fall 2003 Lecture

CSE 477 VLSI Digital Circuits Fall 2003 Lecture 01: Introduction Mary Jane Irwin ( www. cse. psu. edu/~mji ) www. cse. psu. edu/~cg 477 [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, © 2003 Rabaey, A. Chandrakasan, B. Nikolic] CSE 477 L 01 Introduction. 1 J. Irwin&Vijay, PSU, 2003

Course Contents q Introduction to digital integrated circuits l q Course goals l q CMOS devices and manufacturing technology. CMOS logic gates and their layout. Propagation delay, noise margins, and power dissipation. Combinational (e. g. , arithmetic) and sequential circuit design. Memory circuit design. Ability to design and implement CMOS digital circuits and optimize them with respect to different constraints: size (cost), speed, power dissipation, and reliability Course prerequisites l l EE 310. Electronic Circuit Design CSE 471. Logic Design of Digital Systems CSE 477 L 01 Introduction. 2 Irwin&Vijay, PSU, 2003

Course Administration q Instructor: Mary Jane Irwin mji@cse. psu. edu www. cse. psu. edu/~mji 227 Pond Lab Office Hrs: T 16: 00 -17: 00 & W 9: 30 -10: 45 q TA: q Labs: Accounts on 101 Pond Lab machines q URL: www. cse. psu. edu/~cg 477 q Text: Digital Integrated Circuits, 2 nd Edition Rabaey et. al. , © 2003 q Slides: pdf on the course web page after lecture Feihui Li feli@cse. psu. edu 128 Hammond Office Hrs: TBD CSE 477 L 01 Introduction. 3 Irwin&Vijay, PSU, 2003

Grading Information q Grade determinates l Midterm Exam ~25% - Monday, October 20 th , 20: 15 to 22: 15, Location TBD l Final Exam ~25% - Monday, December 15 th, 10: 10 to noon, Location TBD l Homeworks/Lab Assignments (5) ~20% - Due at the beginning of class (or, if submitted electronically, by 17: 00 on the due date). No late assignments will be accepted. l l Design Project (teams of ~2) In-class pop quizzes ~25% ~ 5% q Please let me know about exam conflicts ASAP q Grades will be posted on the course homepage l l Must submit email request for change of grade after discussions with the TA (Homeworks/Lab Assignments) or instructor (Exams) December 9 th deadline for filing grade corrections; no requests for grade changes will be accepted after this date CSE 477 L 01 Introduction. 4 Irwin&Vijay, PSU, 2003

Background from CSE 471 and EE 310 q Basic circuit theory l l q Hardware description language l q VHDL or verilog Use of modern EDA tools l l q resistance, capacitance, inductance MOS gate characteristics simulation, synthesis, validation (e. g. , Synopsys) schematic capture tools (e. g. , Logic. Works) Logic design l logical minimization, FSMs, component design CSE 477 L 01 Introduction. 5 Irwin&Vijay, PSU, 2003

Course Structure q Design and tool intensive class l Micromagic (MMI) “max” and “sue” for layout - Online documentation and tutorials q l HSPICE for circuit simulation l unix (Sun/Solaris) operating system environment Lectures: l 2 weeks on the CMOS inverter l 3 weeks on static and dynamic CMOS gates l 2 weeks on C, R, and L effects 2 week on sequential CMOS circuits 2 weeks on design of datapath structures 2 weeks on memory design 1 week on design for test, margining, scaling, trends 1 week exams l l l CSE 477 L 01 Introduction. 6 Irwin&Vijay, PSU, 2003

“Executives might make the final decisions about what would be produced, but engineers would provide most of the ideas for new products. After all, engineers were the people who really knew the state of the art and who were therefore best equipped to prophesy changes in it. ” The Soul of a New Machine, Kidder, pg 35 CSE 477 L 01 Introduction. 7 Irwin&Vijay, PSU, 2003

Transistor Revolution q Transistor –Bardeen (Bell Labs) in 1947 q Bipolar transistor – Schockley in 1949 q First bipolar digital logic gate – Harris in 1956 q First monolithic IC – Jack Kilby in 1959 q First commercial IC logic gates – Fairchild 1960 q TTL – 1962 into the 1990’s q ECL – 1974 into the 1980’s CSE 477 L 01 Introduction. 8 Irwin&Vijay, PSU, 2003

MOSFET Technology q MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935 q CMOS – 1960’s, but plagued with manufacturing problems (used in watches due to their power limitations) q PMOS in 1960’s (calculators) q NMOS in 1970’s (4004, 8080) – for speed q CMOS in 1980’s – preferred MOSFET technology because of power benefits q Bi. CMOS, Gallium-Arsenide, Silicon-Germanium q SOI, Copper-Low K, strained silicon, … CSE 477 L 01 Introduction. 9 Irwin&Vijay, PSU, 2003

Moore’s Law q In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 months (i. e. , grow exponentially with time). q Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s. l 2300 transistors, 1 MHz clock (Intel 4004) - 1971 l 16 Million transistors (Ultra Sparc III) l 42 Million, 2 GHz clock (Intel P 4) - 2001 140 Million transistor (HP PA-8500) l CSE 477 L 01 Introduction. 10 Irwin&Vijay, PSU, 2003

Moore’s Law in Microprocessors # transistors on lead microprocessors double every 2 years 1000 2 X growth in 1. 96 years! Transistors (MT) 100 10 486 1 386 286 0. 1 0. 01 8086 8080 8008 4004 8085 0. 001 1970 CSE 477 L 01 Introduction. 11 P 6 Pentium® proc 1980 1990 Year Courtesy, Intel 2000 2010 Irwin&Vijay, PSU, 2003

Intel 4004 Microprocessor (10000 nm) CSE 477 L 01 Introduction. 12 Irwin&Vijay, PSU, 2003

Intel P 2 Microprocessor (280 nm) CSE 477 L 01 Introduction. 13 Irwin&Vijay, PSU, 2003

State-of-the Art: Lead Microprocessors CSE 477 L 01 Introduction. 14 Irwin&Vijay, PSU, 2003

Die Size Growth Die size grows by 14% to satisfy Moore’s Law Die size (mm) 100 10 8080 8008 4004 8086 8085 286 386 P 6 486 Pentium ® proc ~7% growth per year ~2 X growth in 10 years 1 1970 CSE 477 L 01 Introduction. 16 1980 1990 Year Courtesy, Intel 2000 2010 Irwin&Vijay, PSU, 2003

Clock Frequency Lead microprocessors frequency doubles every 2 years 10000 2 X every 2 years Frequency (Mhz) 1000 P 6 100 486 10 8085 1 0. 1 1970 CSE 477 L 01 Introduction. 17 8086 286 Pentium ® proc 386 8080 8008 4004 1980 1990 Year Courtesy, Intel 2000 2010 Irwin&Vijay, PSU, 2003

Power Dissipation Lead Microprocessors power continues to increase Power (Watts) 100 P 6 Pentium ® proc 10 8086 286 1 8008 4004 486 386 8085 8080 0. 1 1974 1978 1985 1992 2000 Year Power delivery and dissipation will be prohibitive CSE 477 L 01 Introduction. 18 Courtesy, Intel Irwin&Vijay, PSU, 2003

Power Density (W/cm 2) 10000 Rocket Nozzle 1000 Nuclear Reactor 100 8086 10 4004 Hot Plate P 6 8008 8085 Pentium® proc 386 286 486 8080 1 1970 1980 1990 Year 2000 2010 Power density too high to keep junctions at low temp CSE 477 L 01 Introduction. 19 Courtesy, Intel Irwin&Vijay, PSU, 2003

Technology Directions: “Old” SIA Roadmap Year Feature size (nm) Mtrans/cm 2 Chip size (mm 2) Signal pins/chip Clock rate (MHz) Wiring levels Power supply (V) High-perf power (W) Battery power (W) 1999 2002 2005 2008 2011 2014 180 7 170 768 600 6 -7 1. 8 90 1. 4 130 14 -26 170 -214 1024 800 7 -8 1. 5 130 2. 0 100 47 235 1024 1100 8 -9 1. 2 160 2. 4 70 115 269 1280 1400 9 0. 9 170 2. 0 50 284 308 1408 1800 9 -10 0. 6 174 2. 2 35 701 354 1472 2200 10 0. 6 183 2. 4 For Cost-Performance MPU (L 1 on-chip SRAM cache; 32 KB/1999 doubling every two years) http: //public. itrs. net CSE 477 L 01 Introduction. 20 Irwin&Vijay, PSU, 2003

Why Scaling? q Technology shrinks by ~0. 7 per generation q With every generation can integrate 2 x more functions on a chip; chip cost does not increase significantly q Cost of a function decreases by 2 x q But … q l How to design chips with more and more functions? l Design engineering population does not double every two years… Hence, a need for more efficient design methods l Exploit different levels of abstraction CSE 477 L 01 Introduction. 21 Irwin&Vijay, PSU, 2003

Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT Vin Vout G S n+ CSE 477 L 01 Introduction. 22 DEVICE D n+ Irwin&Vijay, PSU, 2003

Major Design Challenges q Microscopic issues l l l q ultra-high speeds power dissipation and supply rail drop growing importance of interconnect noise, crosstalk reliability, manufacturability clock distribution Year 1997 1998 1999 2002 Tech. (nm) 350 250 180 130 CSE 477 L 01 Introduction. 24 Macroscopic issues l l l time-to-market design complexity (millions of gates) high levels of abstractions reuse and IP, portability systems on a chip (So. C) tool interoperability Complexity Frequency 3 Yr. Design Staff Costs Staff Size 13 M Tr. 400 MHz 210 $90 M 20 M Tr. 500 MHz 270 $120 M 32 M Tr. 600 MHz 360 $160 M 130 M Tr. 800 MHz 800 $360 M Irwin&Vijay, PSU, 2003

Next Lecture and Reminders q Next lecture l Design metrics - Reading assignment – 1. 3 q Reminders l Hands on max tutorial - ? Tuesday? evening from 7: 00? to 9: 00? pm in 101 Pond Lab l HW 1 due September 16 th l Project team and title due September 18 th Evening midterm exam scheduled l - Monday, October 20 th , 20: 15 to 22: 15, Location TBD - Please let me know ASAP (via email) if you have a conflict CSE 477 L 01 Introduction. 25 Irwin&Vijay, PSU, 2003