Scaling of MOS Circuits EE 213 VLSI Design

Scaling of MOS Circuits EE 213 VLSI Design

Scaling • VLSI technology is constantly evolving towards smaller line widths • Reduced feature size generally leads to – better / faster performance – More gate / chip • More accurate description of modern technology is ULSI (ultra large scale integration

Scaling Factors • In our discussions we will consider 2 scaling factors, α and β • 1/ β is the scaling factor for VDD and oxide thickness D • 1/ α is scaling factor for all other linear dimensions • We will assume electric field is kept constant

Scaling Factors for Device Parameters • Simple derivations showing the effects of scaling are derived in Pucknell and Eshraghian pages 125 - 129 • It is important that you understand how the following parameters are effected by scaling • • • Gate Area Gate Capacitance per unit area Gate Capacitance Charge in Channel Resistance Transistor Delay Maximum Operating Frequency Transistor Current Switching Energy Power Dissipation Per Gate (Static and Dynamic) Power Dissipation Per Unit Area Power - Speed Product

Scaling of Interconnects • Resistance of track R ~ L / wt • R (scaled) ~ (L / α) / ( (w/ α )* (t /α)) • R(scaled) = αR • therefore resistance increases with scaling A t w L B

Scaling - Time Constant • • • Time constant of track connected to gate, T = R * Cg T(scaled) = α R * (β / α 2) *Cg = (β / α) *R*Cg Let β = α, therefore T is unscaled! Therefore delays in tracks don’t reduce with scaling Therefore as tracks get proportionately larger, effect gets worse • Cross talk between connections gets worse because of reduced spacing