CSE 477 VLSI Digital Circuits Fall 2003 Lecture

CSE 477 VLSI Digital Circuits Fall 2003 Lecture 05: IC Manufacturing Mary Jane Irwin ( www. cse. psu. edu/~mji ) Guest Lecturer: Greg Link www. cse. psu. edu/~cg 477 [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, © 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CSE 477 L 05 IC Manufacturing. 1 Irwin&Vijay, PSU, 2003

Review: CMOS Inverter q Full rail-to-rail swing high noise margins q Low output impedance q High input impedance q No direct path steady-state between power and ground no static power dissipation q Propagation delay a function of load capacitance and on resistance of transistors VDD Vin Vout CL CSE 477 L 05 IC Manufacturing. 2 Irwin&Vijay, PSU, 2003

Growing the Silicon Ingot From Smithsonian, 2000 CSE 477 L 05 IC Manufacturing. 4 Irwin&Vijay, PSU, 2003

CMOS Process at a Glance Define active areas Etch and fill trenches q One full photolithography sequence per layer (mask) Implant well regions q Built (roughly) from the bottom up Deposit and pattern polysilicon layer 5 metal 2 4 metal 1 2 polysilicon Implant source and drain regions and substrate contacts 3 source and drain diffusions exception! 1 tubs (aka wells, active areas) Create contact and via windows Deposit and pattern metal layers CSE 477 L 05 IC Manufacturing. 5 Irwin&Vijay, PSU, 2003

Photolithographic Process optical mask oxidation stepper exposure photoresist removal (ashing) photoresist coating photoresist development process step spin, rinse, dry CSE 477 L 05 IC Manufacturing. 6 acid etch Irwin&Vijay, PSU, 2003

Patterning - Photolithography 1. Oxidation mask UV light 2. Photoresist (PR) coating 3. Stepper exposure 4. Photoresist development and bake Si. O 2 PR 5. Acid etching Unexposed (negative PR) Exposed (positive PR) 6. Spin, rinse, and dry 7. Processing step Ion implantation Plasma etching Metal deposition 8. Photoresist removal CSE 477 (ashing) L 05 IC Manufacturing. 7 Irwin&Vijay, PSU, 2003

Example of Patterning of Si. O 2 Chemical or plasma etch Hardened resist Si. O 2 Si-substrate Silicon base material Photoresist Si. O 2 4. After development and etching of resist, chemical or plasma etch of Si. O 2 Si-substrate 1&2. After oxidation and deposition of negative photoresist UV-light Patterned optical mask Hardened resist Si. O 2 Si-substrate 5. After etching Exposed resist Si-substrate 3. Stepper exposure CSE 477 L 05 IC Manufacturing. 8 Si. O 2 Si-substrate 8. Final result after removal of resist Irwin&Vijay, PSU, 2003

Diffusion and Ion Implantation 1. Area to be doped is exposed (photolithography) 2. Diffusion or Ion implantation CSE 477 L 05 IC Manufacturing. 9 Irwin&Vijay, PSU, 2003

Deposition and Etching 1. Pattern masking (photolithography) 2. Deposit material over entire wafer CVD (Si 3 N 4) chemical deposition (polysilicon) sputtering (Al) 3. Etch away unwanted material wet etching dry (plasma) etching CSE 477 L 05 IC Manufacturing. 10 Irwin&Vijay, PSU, 2003

Planarization: Polishing the Wafers From Smithsonian, 2000 CSE 477 L 05 IC Manufacturing. 11 Irwin&Vijay, PSU, 2003

Self-Aligned Gates 1. Create thin oxide in the “active” regions, thick elsewhere 2. Deposit polysilicon 3. Etch thin oxide from active region (poly acts as a mask for the diffusion) 4. Implant dopant CSE 477 L 05 IC Manufacturing. 12 Irwin&Vijay, PSU, 2003

Simplified CMOS Inverter Process cut line p well CSE 477 L 05 IC Manufacturing. 13 Irwin&Vijay, PSU, 2003

P-Well Mask CSE 477 L 05 IC Manufacturing. 14 Irwin&Vijay, PSU, 2003

Active Mask CSE 477 L 05 IC Manufacturing. 15 Irwin&Vijay, PSU, 2003

Poly Mask CSE 477 L 05 IC Manufacturing. 16 Irwin&Vijay, PSU, 2003

P+ Select Mask CSE 477 L 05 IC Manufacturing. 17 Irwin&Vijay, PSU, 2003

N+ Select Mask CSE 477 L 05 IC Manufacturing. 18 Irwin&Vijay, PSU, 2003

Contact Mask CSE 477 L 05 IC Manufacturing. 19 Irwin&Vijay, PSU, 2003

Metal Mask CSE 477 L 05 IC Manufacturing. 20 Irwin&Vijay, PSU, 2003

A Modern CMOS Process Dual-Well Trench-Isolated CMOS gate oxide field oxide Ti. Si 2 p well Al (Cu) Si. O 2 tungsten Si. O 2 n well p-epi n+ p+ p- CSE 477 L 05 IC Manufacturing. 21 Irwin&Vijay, PSU, 2003

Modern CMOS Process Walk-Through Base material: p+ substrate with p-epi layer p-epi p+ Si. N 34 p-epi p+ p+ CSE 477 L 05 IC Manufacturing. 22 Si. O 2 After deposition of gate-oxide and sacrifical nitride (acts as a buffer layer) After plasma etch of insulating trenches using the inverse of the active area mask Irwin&Vijay, PSU, 2003

CMOS Process Walk-Through, con’t Si. O After trench filling, CMP 2 planarization, and removal of sacrificial nitride n p CSE 477 L 05 IC Manufacturing. 23 After n-well and VTp adjust implants After p-well and VTn adjust implants Irwin&Vijay, PSU, 2003

CMOS Process Walk-Through, con’t poly(silicon) After polysilicon deposition and etch n+ p+ After n+ source/dram and p+ source/drain implants. These steps also dope the polysilicon. Si. O 2 After deposition of Si. O 2 insulator and contact hole etch CSE 477 L 05 IC Manufacturing. 24 Irwin&Vijay, PSU, 2003

CMOS Process Walk-Through, con’t Al After deposition and patterning of first Al layer. Al Si. O 2 After deposition of Si. O 2 insulator, etching of via’s, deposition and patterning of second layer of Al. CSE 477 L 05 IC Manufacturing. 25 Irwin&Vijay, PSU, 2003

Layout Editor: max Design Frame CSE 477 L 05 IC Manufacturing. 26 Irwin&Vijay, PSU, 2003

max Layer Representation q CSE 477 L 05 IC Manufacturing. 27 Metals (five) and vias/contacts between the interconnect levels l Note that m 5 connects only to m 4, m 4 only to m 3, etc. , and m 1 only to poly, ndif, and pdif l Some technologies support “stacked vias” q Active – active areas on/in substrate (poly gates, transistor channels (nfet, pfet), source and drain diffusions (ndif, pdif), and well contacts (nwc, pwc)) q Wells (nw) and other select areas (pplus, nplus, prb) Irwin&Vijay, PSU, 2003

CMOS Inverter max Layout Out In metal 1 -poly via metal 1 polysilicon metal 2 VDD pfet pdif PMOS (4/. 24 = 16/1) NMOS (2/. 24 = 8/1) metal 1 -diff via ndif nfet GND metal 2 -metal 1 via CSE 477 L 05 IC Manufacturing. 28 Irwin&Vijay, PSU, 2003

Simplified Layouts in max q Online design rule checking (DRC) q Automatic fet generation (just overlap poly and diffusion and it creates a transistor) q Simplified via/contact generation l l v 12, v 23, v 34, v 45 ct, nwc, pwc 0. 44 x 0. 44 m 1 0. 3 x 0. 3 ct 0. 44 x 0. 44 poly CSE 477 L 05 IC Manufacturing. 29 Irwin&Vijay, PSU, 2003

Design Rule Checker poly_not_fet to all_diff minimum spacing = 0. 14 um CSE 477 L 05 IC Manufacturing. 30 Irwin&Vijay, PSU, 2003

Design Rules q Interface between the circuit designer and process engineer q Guidelines for constructing process masks q Unit dimension: minimum line width l scalable design rules: lambda parameter l absolute dimensions: micron rules q Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur q A complete set includes l l l set of layers intra-layer: relations between objects in the same layer inter-layer: relations between objects on different layers CSE 477 L 05 IC Manufacturing. 31 Irwin&Vijay, PSU, 2003

Why Have Design Rules? q To be able to tolerate some level of fabrication errors such as 1. Mask misalignment 2. Dust 3. Process parameters (e. g. , lateral diffusion) 4. Rough surfaces CSE 477 L 05 IC Manufacturing. 32 Irwin&Vijay, PSU, 2003

Intra-Layer Design Rule Origins q Minimum dimensions (e. g. , widths) of objects on each layer to maintain that object after fab l q minimum line width is set by the resolution of the patterning process (photolithography) Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab 0. 3 micron 0. 15 CSE 477 L 05 IC Manufacturing. 33 0. 3 micron Irwin&Vijay, PSU, 2003

Inter-Layer Design Rule Origins 1. Transistor rules – transistor formed by overlap of active and poly layers Transistors Catastrophic error Unrelated Poly & Diffusion Thinner diffusion, but still working CSE 477 L 05 IC Manufacturing. 34 Irwin&Vijay, PSU, 2003

Transistor Layout CSE 477 L 05 IC Manufacturing. 35 Irwin&Vijay, PSU, 2003

Inter-Layer Design Rule Origins, Con’t 2. Contact and via rules both materials M 1 contact to p-diffusion M 1 contact to n-diffusion M 1 contact to poly Contact Mask Mx contact to My Via Masks 0. 3 mask misaligned Contact: 0. 44 x 0. 44 0. 14 CSE 477 L 05 IC Manufacturing. 36 Irwin&Vijay, PSU, 2003

Next Lecture and Reminders q Next lecture l Static complementary CMOS gate design - Reading assignment – Rabaey, et al, 6. 1 -6. 2. 1 q Reminders l HW 2 due September xxth l Evening midterm exam scheduled - Monday, October 20 th , 20: 15 to 22: 15, Location TBD - Please let me know ASAP (via email) if you have a conflict – Only one midterm conflict filed for so far CSE 477 L 05 IC Manufacturing. 37 Irwin&Vijay, PSU, 2003