CSE 477 VLSI Digital Circuits Fall 2003 Lecture

CSE 477 VLSI Digital Circuits Fall 2003 Lecture 10: The Inverter, A Dynamic View Mary Jane Irwin ( www. cse. psu. edu/~mji ) www. cse. psu. edu/~cg 477 [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, © 2003 Rabaey, A. Chandrakasan, B. Nikolic] CSE 477 L 10 Inverter, Dynamic. 1 J. Irwin&Vijay, PSU, 2003

Inverter Propagation Delay q Propagation delay is proportional to the time-constant of the network formed by the pull-down resistor and the load capacitance VDD tp. HL = f(Rn, CL) Vout = 0 Rn CL Vin = V DD q tp. HL = ln(2) Reqn CL = 0. 69 Reqn CL tp. LH = ln(2) Reqp CL = 0. 69 Reqp CL tp = (tp. HL + tp. LH)/2 = 0. 69 CL(Reqn + Reqp)/2 To equalize rise and fall times make the on-resistance of the NMOS and PMOS approximately equal. CSE 477 L 10 Inverter, Dynamic. 2 Irwin&Vijay, PSU, 2003

Inverter Transient Response VDD=2. 5 V 0. 25 m W/Ln = 1. 5 W/Lp = 4. 5 Reqn= 13 k ( 1. 5) Reqp= 31 k ( 4. 5) Vout (V) Vin tp. HL tf tp. LH tr tp. HL = 36 psec tp. LH = 29 psec so tp = 32. 5 psec t (sec) From simulation: tp. HL = 39. 9 psec and CSE 477 L 10 Inverter, Dynamic. 4 x 10 -10 tp. LH = 31. 7 psec Irwin&Vijay, PSU, 2003

Inverter Propagation Delay, Revisited q To see how a designer can optimize the delay of a gate have to expand the Req in the delay equation tp. HL = 0. 69 Reqn CL = 0. 69 (3/4 (CL VDD)/IDSATn ) 0. 52 CL / (W/Ln k’n VDSATn ) CSE 477 L 10 Inverter, Dynamic. 5 Irwin&Vijay, PSU, 2003

Design for Performance Increase W/L ratio of the transistor l l q Reduce CL l keep drain diffusions small l limit interconnect capacitance limit fan-out l q the most powerful and effective performance optimization tool in the hands of the designer watch out for self-loading! – when the intrinsic capacitance dominates the extrinsic capacitance Increase VDD l l l tp(normalized) q trade-off energy for performance increasing VDD above a certain level yields minimal improvements reliability concerns enforce a firm upper bound on VDD CSE 477 L 10 Inverter, Dynamic. 6 VDD (V) Irwin&Vijay, PSU, 2003

Impacts of NMOS/PMOS Ratio q So far have sized the PMOS and NMOS so that the Req’s match (ratio of 3 to 3. 5) l l q symmetrical VTC equal high-to-low and low-to-high propagation delays If speed is the only concern, reduce the width of the PMOS device! l widening the PMOS degrades the tp. HL due to larger intrinsic capacitance = (W/Lp)/(W/Ln) r = Reqp/Reqn (resistance ratio of identically-sized PMOS and NMOS) opt = r when wiring capacitance is negligible CSE 477 L 10 Inverter, Dynamic. 7 Irwin&Vijay, PSU, 2003

PMOS/NMOS Ratio Effects x 10 -11 = (W/Lp)/(W/Ln) tp. LH tp. HL tp(sec) tp of 2. 4 (= 31 k /13 k ) gives symmetrical response of 1. 6 to 1. 9 gives optimal performance = (W/Lp)/(W/Ln) CSE 477 L 10 Inverter, Dynamic. 8 Irwin&Vijay, PSU, 2003

Device Sizing for Performance q Divide capacitive load, CL, into Cint : intrinsic - diffusion and Miller effect (Cg) Cext : extrinsic - wiring and fanout l l tp = 0. 69 Req Cint (1 + Cext/Cint) = tp 0 (1 + Cext/Cint) where tp 0 = 0. 69 Req Cint is the intrinsic (unloaded) delay of the gate l q Widening both PMOS and NMOS by a factor S reduces Req by an identical factor (Req = Rref/S), but raises the intrinsic capacitance by the same factor (Cint = SCiref) tp = 0. 69 Rref Ciref (1 + Cext/(SCiref)) = tp 0(1 + Cext/(SCiref)) l tp 0 is independent of the sizing of the gate; with no load the drive of the gate is totally offset by the increased capacitance l any S sufficiently larger than (Cext/Cint) yields the best performance gains with least area impact CSE 477 L 10 Inverter, Dynamic. 9 Irwin&Vijay, PSU, 2003

Sizing Impacts on Delay x 10 -11 tp(sec) for a fixed load S CSE 477 L 10 Inverter, Dynamic. 10 The majority of the improvement is already obtained for S = 5. Sizing factors larger than 10 barely yield any extra gain (and cost significantly more area). self-loading effect (intrinsic capacitance dominates) Irwin&Vijay, PSU, 2003

Impact of Fanout on Delay tp = = tp 0 (1 + Cext/Cint) q q Extrinsic capacitance, Cext, is a function of the fanout of the gate - the larger the fanout, the larger the external load. First determine the input loading effect of the inverter. Both Cg and Cint are proportional to the gate sizing, so Cint = Cg is independent of gate sizing and tp = tp 0 (1 + Cext/ Cg) = tp 0 (1 + f/ ) q The delay of an inverter is a function of the ratio between its external load capacitance and its input gate capacitance, or the gate’s effective fan-out f f = Cext/Cg CSE 477 L 10 Inverter, Dynamic. 11 Irwin&Vijay, PSU, 2003

Inverter Chain q Real goal is to minimize the delay through an inverter chain In Out Cg, 1 1 2 N CL the delay of the j-th inverter stage is tp, j = tp 0 (1 + Cg, j+1/( Cg, j)) = tp 0(1 + fj/ ) and tp = tp 1 + tp 2 +. . . + tp. N so tp = tp, j = tp 0 (1 + Cg, j+1/( Cg, j)) q If CL is given l l How should the inverters be sized? How many stages are needed to minimize the delay? CSE 477 L 10 Inverter, Dynamic. 12 Irwin&Vijay, PSU, 2003

Sizing the Inverters in the Chain q The optimum size of each inverter is the geometric mean of its neighbors – meaning that if each inverter is sized up by the same factor f wrt the preceding gate, it will have the same effective fan-out and the same delay N N f = CL/Cg, 1 = F where the overall effective fan-out of the circuit is F = CL/Cg, 1 and the minimum delay through the inverter chain is N tp = N tp 0 (1 + ( F ) / ) q The relationship between tp and F is linear for one inverter, square root for two, etc. CSE 477 L 10 Inverter, Dynamic. 13 Irwin&Vijay, PSU, 2003

Example of Inverter Chain Sizing In Out Cg, 1 q 1 f=2 f 2 = 4 CL = 8 Cg, 1 CL/Cg, 1 has to be evenly distributed over N = 3 inverters F = CL/Cg, 1 = 8/1 3 f = 8 = 2 CSE 477 L 10 Inverter, Dynamic. 15 Irwin&Vijay, PSU, 2003

Determining N: Optimal Number of Inverters q What is the optimal value for N given F (= f. N) ? l l q if the number of stages is too large, the intrinsic delay of the stages becomes dominate if the number of stages is too small, the effective fan-out of each stage becomes dominate The optimum N is found by differentiating the minimum delay expression divided by the number of stages and setting the result to 0, giving N N + F - ( F ln(F))/N = 0 and f = e(1 + /f) q For = 0 (ignoring self-loading) N = ln(F) and the effective-fan out (tapering factor) is f = e = 2. 718 q For = 1 (the typical case) N = ln(F) - 1 and the effective fan-out (tapering factor) is f = 3. 6 CSE 477 L 10 Inverter, Dynamic. 16 Irwin&Vijay, PSU, 2003

fopt normalized delay Optimum Effective Fan-Out q f Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area). l l So it is common practice to use f = 4 (for = 1) and reduce N Too many stages has a substantial negative impact on delay CSE 477 L 10 Inverter, Dynamic. 17 Irwin&Vijay, PSU, 2003

Example of Inverter (Buffer) Staging F = 64 N = ln(F) – 1 = 3. 16 1 Cg, 1 = 1 CL = 64 Cg, 1 8 1 Cg, 1 = 1 16 Cg, 1 = 1 1 f tp 1 64 65 2 8 18 3 4 15 4 2. 8 15. 3 CL = 64 Cg, 1 4 1 N 2. 8 Cg, 1 = 1 CSE 477 L 10 Inverter, Dynamic. 18 CL = 64 Cg, 1 8 22. 6 CL = 64 Cg, 1 Irwin&Vijay, PSU, 2003

Impact of Buffer Staging for Large CL F ( = 1) 10 q Unbuffered Two Stage Chain 11 8. 3 Opt. Inverter Chain 8. 3 100 101 22 16. 5 1, 000 1001 65 24. 8 10, 000 10, 001 202 33. 1 Impressive speed-ups with optimized cascaded inverter chain for very large capacitive loads. CSE 477 L 10 Inverter, Dynamic. 19 Irwin&Vijay, PSU, 2003

Input Signal Rise/Fall Time In reality, the input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging CL and impacts propagation delay. x 10 -11 tp(sec) q q tp increases linearly with increasing input slope, ts, once ts > tp q ts is due to the limited driving capability of the preceding gate CSE 477 L 10 Inverter, Dynamic. 20 ts(sec) x 10 -11 for a minimum-size inverter with a fan-out of a single gate Irwin&Vijay, PSU, 2003

Design Challenge q A gate is never designed in isolation: its performance is affected by both the fan-out and the driving strength of the gate(s) feeding its inputs. tip = tistep + ti-1 step q Keep signal rise times smaller than or equal to the gate propagation delays. l l q ( 0. 25) good for performance good for power consumption Keeping rise and fall times of the signals small and of approximately equal values is one of the major challenges in high-performance designs - slope engineering. CSE 477 L 10 Inverter, Dynamic. 21 Irwin&Vijay, PSU, 2003

Delay with Long Interconnects q When gates are farther apart, wire capacitance and resistance can no longer be ignored. (rw, cw, L) Vin cint Vout cfan tp = 0. 69 Rdr. Cint + (0. 69 Rdr+0. 38 Rw)Cw + 0. 69(Rdr+Rw)Cfan where Rdr = (Reqn + Reqp)/2 = 0. 69 Rdr(Cint+Cfan) + 0. 69(Rdrcw+rw. Cfan)L + 0. 38 rwcw. L 2 q Wire delay rapidly becomes the dominate factor (due to the quadratic term) in the delay budget for longer wires. CSE 477 L 10 Inverter, Dynamic. 22 Irwin&Vijay, PSU, 2003

Next Lecture and Reminders q Next lecture l Designing fast logic - Reading assignment – Rabaey, et al, 6. 2. 1 q Reminders l Project specs due (on-line) October 9 th l HW#3 due October 16 th l HW#4 due November 11 th (not Nov 4 th as on outline) l HW#5 will be optional (due November 20 th) l Evening midterm exam scheduled - Monday, October 20 th , 20: 15 to 22: 15, Location TBD - Only one midterm conflict scheduled CSE 477 L 10 Inverter, Dynamic. 23 Irwin&Vijay, PSU, 2003