CSE 477 VLSI Digital Circuits Fall 2003 Lecture

CSE 477 VLSI Digital Circuits Fall 2003 Lecture 09: Resistance Mary Jane Irwin ( www. cse. psu. edu/~mji ) www. cse. psu. edu/~cg 477 [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, © 2003 Rabaey, A. Chandrakasan, B. Nikolic] CSE 477 L 09 Resistance. 1 J. Irwin&Vijay, PSU, 2003

CMOS Inverter: Dynamic q Transient, or dynamic, response determines the maximum speed at which a device can be operated. VDD Last lecture’s focus Vout = 0 CL Rn Vin = V DD CSE 477 L 09 Resistance. 2 tp. HL = f(Rn, CL) Today’s focus Irwin&Vijay, PSU, 2003

Review: Sources of Capacitance Vout Vin CL CG 4 M 2 Vin Vout 2 CGD 12 M 1 M 4 CDB 2 CDB 1 Vout 2 Cw CG 3 M 3 intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance CSE 477 L 09 Resistance. 3 Irwin&Vijay, PSU, 2003

Review: Components of CL (0. 25 m) C Term CGD 1 Expression 2 C on W n Value (f. F) H L L H 0. 23 CGD 2 2 C op W p 0. 61 CDB 1 Keqbpn. ADn. Cj + Keqswn. PDn. Cjsw 0. 66 0. 90 CDB 2 Keqbpp. ADp. Cj + Keqswp. PDp. Cjsw 1. 5 1. 15 CG 3 (2 Con)Wn + Cox. Wn. Ln 0. 76 CG 4 (2 Cop)Wp + Cox. Wp. Lp 2. 28 Cw from extraction 0. 12 CL 6. 1 6. 0 CSE 477 L 09 Resistance. 4 Irwin&Vijay, PSU, 2003

Sources of Resistance Top view Poly Gate Drain n+ Source n+ W L q MOS structure resistance - Ron q Source and drain resistance q Contact (via) resistance q Wiring resistance CSE 477 L 09 Resistance. 5 Irwin&Vijay, PSU, 2003

MOS Structure Resistance q The simplest model assumes the transistor is a switch with an infinite “off” resistance and a finite “on” resistance Ron VGS VT S q Ron D However Ron is nonlinear, so use instead the average value of the resistances, Req, at the end-points of the transition (VDD and VDD/2) Req = ½ (Ron(t 1) + Ron(t 2)) Req = ¾ VDD/IDSAT (1 – 5/6 VDD) CSE 477 L 09 Resistance. 6 Irwin&Vijay, PSU, 2003

Equivalent MOS Structure Resistance q q The on resistance is inversely proportional to W/L. Doubling W halves Req For VDD>>VT+VDSAT/2, Req is independent of VDD (see plot). Only a minor improvement in Req occurs when VDD is increased (due to channel length modulation) Once the supply voltage approaches VT, Req increases dramatically x 105 (for VGS = VDD, VDS = VDD/2) Req (Ohm) q VDD (V) VDD(V) NMOS(k ) PMOS (k ) 1 35 115 1. 5 19 55 2 15 38 2. 5 13 31 Req (for W/L = 1), for larger devices divide Req by W/L CSE 477 L 09 Resistance. 7 Irwin&Vijay, PSU, 2003

Source and Drain Resistance G D S RS RD RS, D = (LS, D/W)R where LS, D is the length of the source or drain diffusion R is the sheet resistance of the source or drain diffusion (20 to 100 / ) q More pronounced with scaling since junctions are shallower q With silicidation R is reduced to the range 1 to 4 / CSE 477 L 09 Resistance. 8 Irwin&Vijay, PSU, 2003

Contact Resistance q Transitions between routing layers (contacts through via’s) add extra resistance to a wire l l l q reduce contact resistance by making vias larger (beware of current crowding that puts a practical limit on the size of vias) or by using multiple minimum-size vias to make the contact Typical contact resistances, RC, (minimum-size) l l q keep signals wires on a single layer whenever possible avoid excess contacts 5 to 20 for metal or poly to n+, p+ diffusion and metal to poly 1 to 5 for metal to metal contacts More pronounced with scaling since contact openings are smaller CSE 477 L 09 Resistance. 9 Irwin&Vijay, PSU, 2003

Wire Resistance L H L R= A Sheet Resistance R R 1� = = L HW R 2� = W Material Silver (Ag) Copper (Cu) Gold (Au) Aluminum (Al) Tungsten (W) CSE 477 L 09 Resistance. 10 ( -m) 1. 6 x 10 -8 1. 7 x 10 -8 2. 2 x 10 -8 2. 7 x 10 -8 5. 5 x 10 -8 Sheet Res. ( / ) Material n, p well diffusion 1000 to 1500 n+, p+ diffusion 50 to 150 n+, p+ diffusion 3 to 5 with silicide polysilicon 150 to 200 polysilicon with 4 to 5 silicide Aluminum 0. 05 to 0. 1 Irwin&Vijay, PSU, 2003

Skin Effect At high frequency, currents tend to flow primarily on the surface of a conductor with the current density falling off exponentially with depth into the wire q W = ( /( f )) H where f is frequency = 4 x 10 -7 H/m = 2. 6 m for Al at 1 GHz so the overall cross section is ~ 2(W+H) q The onset of skin effect is at fs - where the skin depth is equal to half the largest dimension of the wire. fs = 4 / ( (max(W, H))2) q An issue for high frequency, wide (tall) wires (i. e. , clocks!) CSE 477 L 09 Resistance. 11 Irwin&Vijay, PSU, 2003

Skin Effect for Different W’s for H =. 70 um 1 E 8 q 1 E 9 1 E 10 A 30% increase in resistance is observe for 20 m Al wires at 1 GHz (versus only a 1% increase for 1 m wires) CSE 477 L 09 Resistance. 12 Irwin&Vijay, PSU, 2003

The Wire transmitters schematic CSE 477 L 09 Resistance. 13 receivers physical Irwin&Vijay, PSU, 2003

Wire Models q Interconnect parasitics (capacitance, resistance, and inductance) l reduce reliability l affect performance and power consumption All-inclusive (C, R, l) model CSE 477 L 09 Resistance. 14 Capacitance-only Irwin&Vijay, PSU, 2003

Parasitic Simplifications q Inductive effects can be ignored l l if the resistance of the wire is substantial enough (as is the case for long Al wires with small cross section) if the rise and fall times of the applied signals are slow enough q When the wire is short, or the cross-section is large, or the interconnect material has low resistivity, a capacitance only model can be used q When the separation between neighboring wires is large, or when the wires run together for only a short distance, interwire capacitance can be ignored and all the parasitic capacitance can be modeled as capacitance to ground CSE 477 L 09 Resistance. 15 Irwin&Vijay, PSU, 2003

Simulated Wire Delays L Vin L/4 L/2 L voltage (V) L/10 Vout time (nsec) CSE 477 L 09 Resistance. 16 Irwin&Vijay, PSU, 2003

Wire Delay Models q Ideal wire l l q same voltage is present at every segment of the wire at every point in time - at equi-potential only holds for very short wires, i. e. , interconnects between very nearest neighbor gates Lumped C model l when only a single parasitic component (C, R, or L) is dominant the different fractions are lumped into a single circuit element Driver - When the resistive component is small and the switching frequency is low to medium, can consider only C; the wire itself does not introduce any delay; the only impact on performance comes from wire capacitance Vout RDriver Vout Clumped cwire capacitance per unit length l good for short wires; pessimistic and inaccurate for long wires CSE 477 L 09 Resistance. 17 Irwin&Vijay, PSU, 2003

Wire Delay Models, con’t q Lumped RC model l l q total wire resistance is lumped into a single R and total capacitance into a single C good for short wires; pessimistic and inaccurate for long wires Distributed RC model l circuit parasitics are distributed along the length, L, of the wire - c and r are the capacitance and resistance per unit length Vin r L c L l r L c L VN c L (r, c, L) Vin VN Delay is determined using the Elmore delay equation N Di = ckrik k=1 CSE 477 L 09 Resistance. 18 Irwin&Vijay, PSU, 2003

RC Tree Definitions q RC tree characteristics l A unique resistive path exists between the source node and any node of the network s r 2 1 c 1 - Single input (source) node, s - All capacitors are between a node and GND - No resistive loops l r 1 2 c 2 r 3 4 r 4 3 c 4 ri i Path resistance (sum of the resistances on the path from the input node to node i) ci i rii = rj (rj [path(s i)] j=1 l Shared path resistance (resistance shared along the paths from the input node to nodes i and k) N rik = rj (rj [path(s i) path(s k)]) j=1 q A typical wire is a chain network with (simplified) Elmore N delay of DN = cirii CSE 477 L 09 Resistance. 19 i=1 Irwin&Vijay, PSU, 2003

Chain Network Elmore Delay D 1=c 1 r 1 1 Vin c 1 r 2 D 2=c 1 r 1 + c 2(r 1+r 2) 2 c 2 ri-1 ci-1 ri r. N i ci N VN c. N Di=c 1 r 1+ c 2(r 1+r 2)+…+ci(r 1+r 2+…+ri) Elmore delay equation N i DN = cirii = ci rj Di=c 1 req+ 2 c 2 req+ 3 c 3 req+…+ icireq CSE 477 L 09 Resistance. 21 Irwin&Vijay, PSU, 2003

Elmore Delay Models Uses q Modeling the delay of a wire q Modeling the delay of a series of pass transistors q Modeling the delay of a pull-up and pull-down networks CSE 477 L 09 Resistance. 22 Irwin&Vijay, PSU, 2003

Distributed RC Model for Simple Wires q A length L RC wire can be modeled by N segments of length L/N l The resistance and capacitance of each segment are given by r L/N and c L/N DN = (L/N)2(cr+2 cr+…+Ncr) = (cr. L 2) (N(N+1))/(2 N 2) = CR((N+1)/(2 N)) where R (= r. L) and C (= c. L) are the total lumped resistance and capacitance of the wire q For large N DN = RC/2 = rc. L 2/2 l Delay of a wire is a quadratic function of its length, L l The delay is 1/2 of that predicted (by the lumped model) CSE 477 L 09 Resistance. 23 Irwin&Vijay, PSU, 2003

Step Response Points Voltage Range Lumped RC Distributed RC 0 50% (tp) 0. 69 RC 0. 38 RC 0 63% ( ) RC 0. 5 RC 10% 90% (tr) 2. 2 RC 0. 9 RC 0 90% 2. 3 RC 1. 0 RC q Time to reach the 50% point is t = ln(2) = 0. 69 Time to reach the 90% point is t = ln(9) = 2. 2 Example: Consider a Al 1 wire 10 cm long and 1 m wide l l Using a lumped C only model with a source resistance (RDriver) of 10 k and a total lumped capacitance (Clumped) of 11 p. F t 50% = 0. 69 x 10 k x 11 p. F = 76 ns t 90% = 2. 2 x 10 k x 11 p. F = 242 ns Using a distributed RC model with c = 110 a. F/ m and r = 0. 075 / m t 50% = 0. 38 x (0. 075 / m) x (110 a. F/ m) x (105 m)2 = 31. 4 ns t 90% = 0. 9 x (0. 075 / m) x (110 a. F/ m) x (105 m)2 = 74. 25 ns Poly: t 50% = 0. 38 x (150 / m) x (88+2 54 a. F/ m) x (105 m)2 = 112 s Al 5: t 50% = 0. 38 x (0. 0375 / m) x (5. 2+2 12 a. F/ m) x (105 m)2 = 4. 2 ns CSE 477 L 09 Resistance. 24 Irwin&Vijay, PSU, 2003

Putting It All Together RDriver rw, cw, L Vout Vin q Total propagation delay consider driver and wire D = RDriver. Cw + (Rw. Cw)/2 = RDriver. Cw + 0. 5 rwcw. L 2 and tp = 0. 69 RDriver. Cw + 0. 38 Rw. Cw where Rw = rw. L and Cw = cw. L q The delay introduced by wire resistance becomes dominant when (Rw. Cw)/2 RDriver CW (when L 2 RDriver/Rw) l For an RDriver = 1 k driving an 1 m wide Al 1 wire, Lcrit is 2. 67 cm CSE 477 L 09 Resistance. 25 Irwin&Vijay, PSU, 2003

Design Rules of Thumb q rc delays should be considered when tp. RC > tpgate of the driving gate Lcrit > (tpgate/0. 38 rc) l q actual Lcrit depends upon the size of the driving gate and the interconnect material rc delays should be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line trise < RC l when not met, the change in the signal is slower than the propagation delay of the wire so a lumped C model suffices CSE 477 L 09 Resistance. 26 Irwin&Vijay, PSU, 2003

Nature of Interconnect Global Interconnect Source: Intel CSE 477 L 09 Resistance. 27 Irwin&Vijay, PSU, 2003

Overcoming Interconnect Resistance q Selective technology scaling l q scale W while holding H constant Use better interconnect materials l lower resistivity materials like copper - As processes shrink, wires get shorter (reducing C) but they get closer together (increasing C) and narrower (increasing R). So RC wire delay increases and capacitive coupling gets worse. - Copper has about 40% lower resistivity than aluminum, so copper wires can be thinner (reducing C) without increasing R l use silicides (WSi 2, Ti. Si 2, Pt. Si 2 and Ta. Si) silicide - Conductivity is 8 -10 times better than poly alone polysilicon Si. O 2 n+ q Use more interconnect layers l p n+ reduces the average wire length L (but beware of extra contacts) CSE 477 L 09 Resistance. 28 Irwin&Vijay, PSU, 2003

Wire Spacing Comparisons Intel P 858 Al, 0. 18 m Intel P 856. 5 Al, 0. 25 m - 0. 07 - 0. 05 - 0. 12 M 4 - 0. 33 M 3 - 0. 33 M 2 Scale: 2, 160 nm CSE 477 L 09 Resistance. 29 M 6 M 5 - 0. 08 - 1. 11 IBM CMOS-8 S CU, 0. 18 m M 1 - 0. 17 M 5 M 4 - 0. 49 M 3 - 0. 49 M 2 - 1. 00 M 1 - 0. 10 M 7 - 0. 10 M 6 - 0. 50 M 5 - 0. 50 M 4 - 0. 50 M 3 - 0. 70 M 2 - 0. 97 M 1 From MPR, 2000 Irwin&Vijay, PSU, 2003

Comparison of Wire Delays From MPR, 2000 CSE 477 L 09 Resistance. 30 Irwin&Vijay, PSU, 2003

Inductance q When the rise and fall times of the signal become comparable to the time of flight of the signal waveform across the line, then the inductance of the wire starts to dominate the delay behavior Vin l r g q l r c g c Vout Must consider wire transmission line effects l Signal propagates over the wire as a wave (rather than diffusing as in rc only models) - Signal propagates by alternately transferring energy from capacitive to inductive modes CSE 477 L 09 Resistance. 31 Irwin&Vijay, PSU, 2003

More Design Rules of Thumb q Transmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight) tr (tf) < 2. 5 tflight = 2. 5 L/v l q For on-chip wires with a maximum length of 1 cm, we only worry about transmission line effects when tr < 150 ps Transmission line effects should only be considered when the total resistance of the wire is limited R < 5 Z 0 = 5 (V/I) CSE 477 L 09 Resistance. 32 Irwin&Vijay, PSU, 2003

Next Lecture and Reminders q Next lecture l The CMOS inverter dynamic view - Reading assignment – Rabaey, et al, 5. 4. 2 -5. 4. 3 q Reminders l Project specs due (on-line) October 9 th l HW#3 due October 16 th l HW#4 due November 11 th (not Nov 4 th as on outline) l HW#5 will be optional (due November 20 th) l Evening midterm exam scheduled - Monday, October 20 th , 20: 15 to 22: 15, Location TBD - Only one midterm conflict scheduled CSE 477 L 09 Resistance. 33 Irwin&Vijay, PSU, 2003