CSE 477 VLSI Digital Circuits Fall 2003 Lecture

CSE 477 VLSI Digital Circuits Fall 2003 Lecture 18: Dynamic Sequential Circuits Mary Jane Irwin ( www. cse. psu. edu/~mji ) www. cse. psu. edu/~cg 477 [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, © 2003 Rabaey, A. Chandrakasan, B. Nikolic] CSE 477 L 18 Dynamic Sequential Logic. 1 J. Irwin&Vijay, PSU, 2003

Review: Sequential Definitions q Static versus dynamic storage l l q static uses a bistable element with feedback (regeneration) and thus preserves its state as long as the power is on static is preferred when updates are infrequent (clock gating) l dynamic stores state on parasitic capacitors so only holds the state for a period of time (milliseconds) and requires periodic refresh l dynamic is usually simpler (fewer transistors), higher speed, lower power Latch versus flipflop l l latches are level sensitive with two modes: transparent - inputs are passed to Q and hold - output stable fliplflops are edge sensitive that only sample the inputs on a clock transition CSE 477 L 18 Dynamic Sequential Logic. 2 Irwin&Vijay, PSU, 2003

Review: Timing Metrics In Out clock tsu In time thold data stable time tc-q Out D Q output stable time CSE 477 L 18 Dynamic Sequential Logic. 3 Irwin&Vijay, PSU, 2003

Review: System Timing Constraints Current State Combinational Logic State Registers Inputs Outputs Next State T (clock period) clock tcdreg + tcdlogic thold CSE 477 L 18 Dynamic Sequential Logic. 4 T tc-q + tplogic + tsu Irwin&Vijay, PSU, 2003

You spend all this time designing one machine and it’s only a hot box for two years, and it has all the useful life of a washing machine. The Soul of a New Machine, Kidder, pg. 239 CSE 477 L 18 Dynamic Sequential Logic. 5 Irwin&Vijay, PSU, 2003

Dynamic ET Flipflop master slave !clk D clk T 1 I 1 QM T 2 C 1 clk master transparent slave hold I 2 Q C 2 !clk tsu = tpd_tx thold = zero tc-q = 2 tpd_inv + tpd_tx clk !clk CSE 477 L 18 Dynamic Sequential Logic. 7 master hold slave transparent Irwin&Vijay, PSU, 2003

Pseudostatic Dynamic Latch q Robustness considerations limit the use of dynamic FF’s l l l q coupling between signal nets and internal storage nodes can inject significant noise and destroy the FF state leakage currents cause state to leak away with time internal dynamic nodes don’t track fluctuations in VDD that reduces noise margins A simple fix is to make the circuit pseudostatic clk QM Q !clk q Add above logic added to all dynamic latches CSE 477 L 18 Dynamic Sequential Logic. 8 Irwin&Vijay, PSU, 2003

Dynamic ET FF Race Conditions !clk D clk T 1 I 1 QM T 2 C 1 clk !clk CSE 477 L 18 Dynamic Sequential Logic. 9 I 2 Q C 2 !clk 0 -0 overlap race condition toverlap 0 -0 < t. T 1 + t. I 1 + t. T 2 1 -1 overlap race condition toverlap 1 -1 < thold Irwin&Vijay, PSU, 2003

Fix 1: Dynamic Two-Phase ET FF clk 1 D clk 2 T 1 I 1 QM T 2 C 1 !clk 1 I 2 Q C 2 !clk 2 master transparent slave hold clk 1 tnon_overlap clk 2 master hold slave transparent CSE 477 L 18 Dynamic Sequential Logic. 10 Irwin&Vijay, PSU, 2003

C 2 MOS (Clocked CMOS) ET Flipflop q A clock-skew insensitive FF Master Slave M 2 clk Mon 4 off D !clk Mon 3 off M 1 master transparent slave hold M 6 QM C 1 !clk Moff 8 on Q Moff 7 on C 2 M 5 clk !clk CSE 477 L 18 Dynamic Sequential Logic. 12 master hold slave transparent Irwin&Vijay, PSU, 2003

C 2 MOS FF 0 -0 Overlap Case q Clock-skew insensitive as long as the rise and fall times of the clock edges are sufficiently small M 2 0 M 4 D M 6 0 QM M 8 Q C 1 C 2 M 1 M 5 clk !clk CSE 477 L 18 Dynamic Sequential Logic. 13 Irwin&Vijay, PSU, 2003

C 2 MOS FF 1 -1 Overlap Case M 2 M 6 QM D 1 M 3 Q C 1 1 M 7 C 2 M 5 clk !clk 1 -1 overlap constraint toverlap 1 -1 < thold CSE 477 L 18 Dynamic Sequential Logic. 14 Irwin&Vijay, PSU, 2003

C 2 MOS Transient Response For a 0. 1 ns clock QM(3) Volts Q(3) Q(0. 1) clk(3) For a 3 ns clock (race condition exists) Time (nsec) CSE 477 L 18 Dynamic Sequential Logic. 15 Irwin&Vijay, PSU, 2003

Pipelining using C 2 MOS clk !clk F In !clk C 1 G clk C 2 Out !clk C 3 aka NORA (NO RAce) Logic What are the constraints on F and G? CSE 477 L 18 Dynamic Sequential Logic. 16 Irwin&Vijay, PSU, 2003

Only Non-Inverting Logic Allowed clk on !clk (off) !clk on clk (off) In = 1 The number of static inversions should be even. CSE 477 L 18 Dynamic Sequential Logic. 17 Irwin&Vijay, PSU, 2003

Fix 3: True Single Phase Clocked (TSPC) Latches Negative Latch In clk Positive Latch clk Q hold when clk = 1 transparent when clk = 0 CSE 477 L 18 Dynamic Sequential Logic. 19 In Q clk transparent when clk = 1 hold when clk = 0 Irwin&Vijay, PSU, 2003

Embedding Logic in TSPC Latch A PUN B Q In clk PDN Q clk A B CSE 477 L 18 Dynamic Sequential Logic. 20 Irwin&Vijay, PSU, 2003

TSPC ET FF Master D clk on off clk master transparent slave hold clk CSE 477 L 18 Dynamic Sequential Logic. 22 Slave on off QM on clk off Q master hold slave transparent Irwin&Vijay, PSU, 2003

Simplified TSPC ET FF M 3 D clk off Mon 6 M 9 QM 1 D clk Mon clk off 2 X !D M 5 off on M 8 clk Moff M 1 M 7 4 on QD master transparent slave hold clk CSE 477 L 18 Dynamic Sequential Logic. 24 master hold slave transparent Irwin&Vijay, PSU, 2003

Sizing Issues in Simplified TSPC ET FF clk !Qmod Volts !Qorig Qmod Transistor sizing Original width M 4, M 5 = 0. 5 m M 7, M 8 = 2 m Modified width M 4, M 5 = 1 m M 7, M 8 = 1 m Time (nsec) CSE 477 L 18 Dynamic Sequential Logic. 25 Irwin&Vijay, PSU, 2003

Split-Output TSPC Latches Negative Latch Positive Latch Q In clk A transparent when clk = 1 hold when clk = 0 When In = 0, A = VDD - VTn CSE 477 L 18 Dynamic Sequential Logic. 26 A In clk Q hold when clk = 1 transparent when clk = 0 When In = 1, A = | VTp | Irwin&Vijay, PSU, 2003

Split-Output TSPC ET FF D clk QM Q clk CSE 477 L 18 Dynamic Sequential Logic. 27 Irwin&Vijay, PSU, 2003

Fix 4: Pulsed FF (AMD-K 6) q Pulse registers - a short pulse (glitch clock) is generated locally from the rising (or falling) edge of the system clock and is used as the clock input to the flipflop l race conditions are avoided by keeping the transparent mode time very short (during the pulse only) l advantage is reduced clock load; disadvantage is substantial increase in verification complexity off clk 1 0 P 1 on X 1 M 3 off on 1/0 D 1 1 M 2 on/ P 2 0 off 1 0 CSE 477 L 18 Dynamic Sequential Logic. 28 M 1 on on !clkd off 0/1 on/off P 3 Q 1/0 M 6 off on M 5 M 4 Irwin&Vijay, PSU, 2003

Fix 5: Sense Amp FF (Strong. Arm SA 100) q Sense amplifier (circuits that accept small swing input signals and amplify them to full rail-to-rail signals) flipflops l advantages are reduced clock load and that it can be used as a receiver for reduced swing differential buses on off on D 1 1 M 9 M 2 M 5 on off on off M 1 M 3 0 CSE 477 L 18 Dynamic Sequential Logic. 29 0 1 1 1 !Q 1 0 M 4 off clk M 7 on off on M 6 M 8 Q 1 1 0 1 M 10 on off on Irwin&Vijay, PSU, 2003

Flipflop Comparison Chart Name Type #clk ld #tr tsu thold Tc-q Mux Static 8 (clk-!clk) 20 3 tpinv+tptx 0 tpinv+tptx Power. PC Static 8 (clk-!clk) 16 2 -phase Ps-Static 8 (clk 1 -clk 2) 16 T-gate Dynamic 4 (clk-!clk) 8 tptx to 1 -1 2 tpinv+tptx C 2 MOS Dynamic 4 (clk-!clk) 8 TSPC Dynamic 4 (clk) 11 tpinv 3 tpinv S-O TSPC Dynamic 2 (clk) 10 AMD K 6 Dynamic 5 (clk) 19 SA 100 Sense. Amp 3 (clk) 20 CSE 477 L 18 Dynamic Sequential Logic. 30 Irwin&Vijay, PSU, 2003

Choosing a Clocking Strategy q Choosing the right clocking scheme affects the functionality, speed, and power of a circuit q Two-phase designs q l + robust and conceptually simple l - need to generate and route two clock signals l - have to design to accommodate possible skew between the two clock signals Single phase designs l l + + + - only need to generate and route one clock signal supported by most automated design methodologies don’t have to worry about skew between the two clocks have to have guaranteed slopes on the clock edges CSE 477 L 18 Dynamic Sequential Logic. 31 Irwin&Vijay, PSU, 2003

Next Lecture and Reminders q Next lecture l Timing issues, Intro to datapath design - Reading assignment – Rabaey, et al, 10. 1 -10. 3. 3; 11. 1 -11. 2 q Reminders l Project prototypes due on-line by 5: 00 pm on Oct 30 th l HW#4 due November 11 th (not Nov 4 th as on outline) l HW#5 will be optional (due November 20 th) l Project final reports due December 4 th l Final exam scheduled - Tuesday, December 16 th from 10: 10 to noon in 118 and 113 Thomas CSE 477 L 18 Dynamic Sequential Logic. 32 Irwin&Vijay, PSU, 2003