Providing Infrastructure for Optical Communication Networks EECS 294

Providing Infrastructure for Optical Communication Networks EECS 294 Colloquium 4 October 2006 Prof. Michael Green Dept. of EECS Henry Samueli School of Engineering mgreen@uci. edu This presentation can be found at: http: //www. eng. uci. edu/faculty/green/public/courses/294

Friday, March 7 2003

Advantages of Optical Fibers over Copper Cable • Very high bandwidth (bandwidth of optical transmission network determined primarily by electronics) • Low loss • Interference Immunity (no antenna-like behavior) • Lower maintenance costs (no corrosion, squirrels don’t like the taste) • Small & light: 1000 feet of copper weighs approx. 300 lb. 1000 feet of fiber weighs approx. 10 lb. • Different light wavelengths can be multiplexed onto a single fiber: Dense Wavelength Division Multiplexing (DWM) • 10 Gb/s transmission networks now being deployed; 40 Gb/s will be here soon.

Protocols for High-Speed Optical Networks Synchronous Optical Network (SONET): • Provides a protocol for long-haul (50 -100 km) wide-area netework (WAN) fiber transmission • Basic OC-1 rate is 51. 84 Mb/s OC-48 (2. 5 Gb/s) & OC-192 (10 Gb/s) are common Gigabit/10 Gigabit Ethernet (IEEE Standard 802. 3): • Ethernet was invented in 1973 at Xerox PARC (“ether” is the name of the medium through which E/M waves were thought to travel) • Provides a protocol for local-area network (LAN) copper or fiber transmission • 1 Gb/s links can be transmitted over twisted-pair copper • 10 Gb/s links can be transmitter over copper (short lengths) or fiber.

Fiber Channel: • Often used for Storage Area Networks (SAN); allows fast transmission of large amounts of data across many different servers. • Currently 1 -4 Gb/s is deployed; 8 Gb/s will arrive soon.

Some SAN Terminology JBOD: Just a Bunch Of Disks Refers to a set of hard disks that are not configured together. RAID: Redundant Array of Independent (or Inexpensive? ) Disks Multiple disk drives that are combined for fault tolerance and performance. Looks like a single disk to the rest of the system. If one disk fails, the systems will continue working properly.

Blade Servers vs. Regular Servers See: http: //www. spectrum. ieee. org/WEBONLY/publicfeature/apr 05/1106 for full article.

Barcelona, Spain: Mare. Nostrum supercomputer cluster (2282 Blade servers) Housed in Chapel Torre Girona (Technical Univ. of Catalonia)

Characteristics of Broadband Signals & Circuits Primarily digital (i. e. , bilevel) operation but high bit rate (multi-Gb/s) dictates analog behavior & design techniques. • Standard analog circuit applications: Ø Continuous-time operation Ø Precision required in signal domain (i. e. , voltage or current) Ø Dynamic range determined by noise & distortion V • Broadband communication circuits: Ø Discrete-time (clocked) operation Ø Precision required in time domain (low jitter) Ø Bilevel signals processed V V t 0 t Vh Vt Vl t t

Typical broadband data waveform: Length of single bit = 1 Unit Interval (1 UI) Eye diagram An eye diagram maps a random bit sequence to a regular structure that can be used to analyze jitter.

Close-up of eye diagram: trise = tfall voltage swing 1 UI Zero crossings

What is Jitter? Jitter is the short-term variation of the significant instants of a digital signal from their ideal positions in time. Jitter normally characterizes variations above 10 Hz; variations below 10 Hz are called wander. The effects of these variations are measured in 3 ways: 1. Phase noise (frequency domain) 2. Jitter (time domain) 3. Bit Error-Rate (end result of phase noise & jitter)

Types of Jitter 1. Random Jitter (RJ) • Originates from external and internal random noise sources • Stochastic in nature (probabilitybased) • Measured in rms units • Observed as Gaussian histogram around zero-crossing • Grows without bound over time Histogram measurement at zero crossing exhibiting Gaussian probability distribution

Types of Jitter (cont. ) 2. Deterministic Jitter (DJ) • Originates from circuit non-idealities (e. g. , finite bandwidth, offset, etc. ) • Amount of DJ at any given transition is predictable • Measured in peak-to-peak units • Bounded and observed in various eye diagram “signatures” • Different types of DJ: a) Intersymbol interference (ISI) b) Duty-cycle distortion (DCD) c) Periodic jitter (PJ)

a) Intersymbol interference (ISI) Consider a 1 UI output pulse from a buffer: 1 UI < 1 UI If rise/fall time << 1 UI, then the output pulse is attenuated and the pulse width decreases.

ISI (cont. ) Consider 2 different bit sequences: 0 0 1 1 0 1 Steady-state not reached at end of 2 nd bit 2 output sequences superimposed ISI is characterized by a double edge in the eye diagram. It is measured in units of ps peak-to-peak. t = ISI

Effect of ISI on eye diagram: Double-edge

b) Duty cycle distortion (DCD) Occurs when rising and falling edges exhibit different delays Caused by circuit mismatches Nominal data sequence Data sequence with early falling edges & late rising edges t = DCD Eye diagram with DCD Crossing offset from nominal threshold

c) Periodic Jitter (PJ) Timing variation caused by periodic sources unrelated to the data pattern. Can be correlated or uncorrelated with data rate. Clock source with duty cycle t 1 t 0 Synchronized data exhibiting correlated PJ Uncorrelated jitter (e. g. , sub-rate PJ due to supply ripple) affects the eye diagram in a similar way as RJ.

Jitter and Bit Error Rate 0 Probability of sample at t > t 0 from left -hand transition: Probability of sample at t < t 0 from right-hand transition: T R

Total Bit Error Rate (BER) given by:

Example: T = 100 ps log(0. 5) log BER t 0 (ps) (64 ps eye opening) (38 ps eye opening)

Bathtub Curves The bit error-rate vs. sampling time can be measured directly using a bit error-rate tester (BERT) at various sampling points. Note: The inherent jitter of the analyzer trigger should be considered.

Benefits of Using Bathtub Curve Measurements 1. Curves can easily be numerically extrapolated to very low BERs (corresponding to random jitter), allowing much lower measurement times. Example: 10 -12 BER with T = 100 ps is equivalent to an average of 1 error per 100 s. To verify this over a sample of 100 errors would require almost 3 hours! t 0 (ps)

2. Deterministic jitter and random jitter can be distinguished and measured by observing the bathtub curve.

Advantages of Using CMOS Fabrication Process • Compact (shared diffusion regions) • Very low static power dissipation • High noise margins (nearly ideal inverter voltage transfer characteristic) • Very well modeled and characterized • Inexpensive (? ) • Mechanically robust • Lends itself very well to high integration levels • Si. Ge Bi. CMOS has many advantages but is a generation behind currently available standard CMOS

CMOS gates generate and are sensitive to supply/ground bounce. Series R & L cause supply/ground bounce. Resulting modulation of transistor Vt’s results in jitter.

data in data out clock in clock out Rs = 5 W Ls = 5 n. H clock out Rs = 0 Ls = 0 clock out Rs = 5 W Ls = 5 n. H data out

Inverter based on differential pair: • Differential operation • Inherent common-mode rejection • Very robust in the presence of common-mode disturbances (e. g. , VDD/VSS bounce) “Current-mode logic (CML)”

data in data out clock in clock out Rs = 5 W Ls = 5 n. H clock out Rs = 0 Ls = 0 clock out Rs = 5 W Ls = 5 n. H data out

Research Topics n Bi. CMOS 10 Gb/s Adaptive Equalizer n A Novel CDR with Adjustable Phase Detector Characteristics n A Distributed Approach to Broadband Circuit Design

Research Topics à Bi. CMOS 10 Gb/s Adaptive Equalizer Evelina Zhang, Graduate Student Researcher n A Novel CDR with Adjustable Phase Detector Characteristics n A Distributed Approach to Broadband Circuit Design

Cable Model Copper Cable +10 0 -10 -20 -30 magnitude (d. B) shorter cable longer cable 1 G 100 M 10 G f phase (deg) 0 shorter cable -100 Where: L is the cable length a is a cable-dependent characteristic -200 -300 100 M longer cable 1 G 10 G f

Motivation n Reduce ISI n input waveform (V) 0. 5 Improve receiver sensitivity 0 0 -0. 5 39 -0. 5 40 41 42 43 0. 3 100 0 t (ns) output waveform (V) 200 300 t (ps) output eye 0. 3 0 -0. 3 39 input eye 0. 5 0 -0. 3 40 41 42 43 t (ns) 0 100 200 300 t (ps)

Adaptive Equalizer Implemented in Jazz Semiconductor Si. Ge process: • 120 GHz f. T npn • 0. 35 m CMOS

Equalizer Block Diagram

Feedforward Path

FFE Frequency Response Vcontrol f (Hz)

ISI & Transition Time VFFE teq = 45 ps PW = 108 ps 0. 3 teq = 60 ps PW = 100 ps 0 -0. 3 2. 4 teq = 75 ps PW = 86 ps 2. 5 2. 6 2. 7 • Simulations indicate that ISI correlates strongly with FFE transition time teq. • Optimum teq is observed to be 60 ps. 2. 8 t (ns)

Slicer

Feedback Path

Transition Time Detector DC characteristic: Transient Characteristic: (b) (a) • Rectification & filtering done in a single stage. t

Integrator

Detector + Integrator From FFE t. FFE slope detector From Slicer tslicer=60 ps slope detector FFE transition Time t. FFE Vcontrol (m. V) 90 ps 60 40 75 ps 20 60 ps 0 -20 45 ps -40 -60 _ + Vcontrol 0 10 20 30 40 50 15 ps t (ns)

System Analysis tslicer detector Kd Vcontrol + _ integrator feedforward equalizer H(s) Keq detector Kd Keq = 1. 5 ps/m. V Kd = 2. 5 m. V/ps tint = 75 ns teq

Measurement Setup EQ inputs Die under test 231 PRBS signal applied to cable EQ outputs

Eye Diagrams EQ input EQ output 4 -foot RU 256 cable 4. 0 ps rms jitter 15 -foot RU 256 cable 3. 9 ps rms jitter

Summary of Measured Performance Supply voltage 3. 3 V Power Dissipation 350 m. W (155 m. W not including output driver) Die Size 0. 81 mm X 0. 87 mm Output Swing 490 m. V single-ended p-p Random Jitter 4. 0 ps rms (4 -foot cable) 3. 9 ps rms (15 -foot cable)

Ongoing Research n Investigate transition detector more thoroughly n Understand trade-off between ISI reduction and random jitter generation n Investigate compensation of PMD in optical fiber

Random noise in Analog Equalizer input eye (no noise added) output eye ISI: 6. 2 ps p-p

input eye with added noise output eye ISI+random jitter: 23 ps p-p ISI is reduced but random jitter is increased due to amplification of random noise.

Decision Feedback Equalization (DFE)

Summing circuit: Variable delay circuit:

DFE Simulations (copper) output eye no noise added ISI: 6. 7 ps p-p output eye random noise added ISI+random jitter: 7. 4 ps p-p

DFE Simulations (fiber) input waveform exhibiting PMD input eye output eye ISI: 7. 9 ps p-p

Research Topics n Bi. CMOS 10 Gb/s Adaptive Equalizer àA Novel CDR with Adjustable Phase Detector Characteristics Xinyu Chen, Graduate Student Researcher n A Distributed Approach to Broadband Circuit Design

Clock/Data Recovery Circuits CDR Requirements: Binary operation Linear operation • • Ability to handle high bit rates Low jitter generation High jitter tolerance Fast acquisition

2 -Loop CDR Architecture Is it possible for a CDR to exhibit linear (quiet) behavior and fast acquisition with a single loop?

“Ternary” latch: Deadband PD characteristic

CML version: external control

Comparisons

Simulation Results Conventional Binary PD Ternary PD; VG = 1. 75 V Hogge PD Ternary PD; VG = 1. 65 V

Varying VG During Acquisition

Future Work n Using the variable PD characteristic as part of a lock detection circuit. n Minimizing jitter in a similar way.

Research Topics n Bi. CMOS 10 Gb/s Adaptive Equalizer n A Novel CDR with Adjustable Phase Detector Characteristics àA Distributed Approach to Broadband Circuit Design Ullas Singh, Graduate Student Researcher

Distributed Amplifier • • Signals travel ballistically through amplifier. Higher gain-bandwidth product. Naturally drives resistive load. Trades off delay for bandwidth.

Distributed Frequency Divider – Buffer delay of lumped elements can be replaced by passive element delay in distributed divider All simulations used 0. 18 m CMOS Lumped frequency divider schematic Distributed divider schematic

Distributed Frequency Divider Simulations Divider sensitivity curve Input/Output waveform

Frequency Divider Layout Area=800 mm*807 mm

Distributed 2 -to-1 Select Circuit Lumped select circuit Proposed distributed select circuit Timing diagram

40 Gb/s MUX Block Diagram 10 Gb/s PRBS generator lumped circuitry 20 Gb/s 4: 2 MUX 2: 1 MUX 40 Gb/s distributed circuitry (180 nm CMOS)

Simulated 40 Gb/s Eye Diagram Vout (V) 0. 6 0. 4 0. 2 0 -0. 2 -0. 4 -0. 6 0 10 20 30 40 50 ISI: 2 ps (80 m. UI) p-p 60 70 80 t (ps)

Test Setup die bonded directly to board

Measured Results Bit-rate: 34 Gb/s (due to varactor variations) Measurements taken with Agilent 86 -100 C DCA-J with 80 GHz plug-in module

Future Research n Analyze nonlinear large-signal effects & derive a clear design methodology. n Investigate possible methods of electrically (or optically? ) controlling characteristic impedances of tranmission lines.