Paul Scherrer Institute Stefan Ritt The PSI DRS

Paul Scherrer Institute Stefan Ritt The PSI DRS 4 Integrated Circuit Chip DPP Workshop PSIClermont March 15 th,

Agenda • Introduction to Switched Capacitor Array Chips – Comparison with FADCs – Overview of chips on the market • The DRS 4 chip – Design principles – Special features – Some applications • New ideas for DRS 5 chip to be designed in 2011 – Increased bandwidth – Zero dead time Stefan Ritt DPP Workshop PSIClermont March 15 th, 2

Introduction to Switched Capacitor Array Chips Stefan Ritt DPP Workshop PSIClermont March 15 th, 3

Detectors in Particle Physics Particles interact with matter and produce light: Signal: ~ 100’s m. V 10 -100 ns Stefan Ritt DPP Workshop PSI March 15 th, 2011 4

Flash ADC Technique PMT/APD Wire Q-sensitive Preamplifier Baseline Shaper Restoration PMT/APD Transimpedance Preamplifier Wire FADC 60 MHz 12 bit Amplitude TDC Time FADC “Fast” 12 bit • • Digital Processing Shaper is used to optimize signals for “slow” 60 MHz FADC Shaping stage can only remove information from the signal Shaping is unnecessary if FADC is “fast” enough All operations (CFD, optimal filtering, integration) can be done digitally Stefan Ritt DPP Workshop PSI March 15 th, 2011 5

Nyquist-Shannon Theorem If a function x(t) contains no frequencies higher than F Hertz, it is completely determined by giving its ordinates at a series of points spaced 1/(2 F) seconds apart. If a detector produces frequencies up to 500 MHz (0. 6 ns rise time), all information from that detector is recorded if sampled at 1 GSPS with good enough signal-to-noise ratio Stefan Ritt DPP Workshop PSI March 15 th, 2011 6

How to measure best timing? Simulation of MCP with realistic noise and different discriminators K. Byrum, H. Frisch, J. -F. Genat et al. , IEEE Trans. Nucl. Sci. 57, 525 (2010) Stefan Ritt DPP Workshop PSI March 15 th, 2011 7

Currently available fast ADCs • • 8 bits – 3 GS/s – 1. 9 W 10 bits – 3 GS/s – 3. 6 W 12 bits – 3. 6 GS/s – 3. 9 W 14 bits – 0. 4 GS/s – 2. 5 W 24 Gbits/s 30 Gbits/s 43. 2 Gbits/s 5. 6 Gbits/s 24 x 1. 8 Gbits/s • Requires high-end FPGA • Complex board design • FPGA power 1. 8 GHz! Stefan Ritt DPP Workshop PSI March 15 th, 2011 8

ADC boards • PX 1500 -4: 2 Channel 3 GS/s 8 bits • ADC 12 D 1 X 00 RB: 1 Channel 1. 8 GS/s 12 bits k 0 -1 l e n n a h c € / 1 Stefan Ritt DPP Workshop PSI March 15 th, 2011 9

Switched Capacitor Array 0. 2 -2 ns Inverter “Domino” ring chain IN Waveform stored Clock Shift Register Out FADC 33 MHz “Time stretcher” GHz MHz Stefan Ritt DPP Workshop PSI March 15 th, 2011 10

Switched Capacitor Array • Cons Dt No continuous acquisition s n • Limited sampling depth o ti a t i • Nonlinear timing im • Dt Dt L e • Pros iz m i n i • High speed (5 GHz) high resolution (11. 5 bit) M : l 2) a • High channel density (9 channels on 5 x 5 mm Go Low power (10 -40 m. W / channel) • Low cost (~ 10€ / channel) • STRAW 3 TARGET AFTER SAM DRS 1 DRS 2 DRS 3 DRS 4 LABRADOR 3 MATACQ G. Varner Univ. of Hawaii Stefan Ritt D. Breton E. Delagnes CEA Saclay DPP Workshop PSI March 15 th, 2011 This talk 11

The DRS 4 Chip Stefan Ritt DPP Workshop PSI March 15 th, 2011 12

Design Options • • CMOS process (typically 0. 35 … 0. 13 mm) sampling speed Number of channels, sampling depth, differential input PLL for frequency stabilization Input buffer or passive input Analog output or (Wilkinson) ADC Internal trigger Exact design of sampling cell PLL Trigger ADC Stefan Ritt DPP Workshop PSI March 15 th, 2011 13

DRS History 1995 Roger Schnyder, Christian Brönnimann, pb DSC Tiny signal 20 p. F 0. 2 p. F 2002 DRS 1 I ~k. T 2004 Temperature Dependence DRS 2 Roberto Dinapoli DRS 3 2007 2008 DRS 4 PLL-regulated Sampling Speed Stefan Ritt DPP Workshop PSI March 15 th, 2011 14

DRS 4 • Fabricated in 0. 25 mm 1 P 5 M MMC process (UMC), 5 x 5 mm 2, radiation hard • 8+1 ch. each 1024 bins, 4 ch. 2048, …, 1 ch. 8192 • Passive differential inputs/outputs • Sampling speed 700 MHz … 5 GHz • On-chip PLL stabilization • Readout speed 30 MHz, multiplexed or in parallel Stefan Ritt DPP Workshop PSIClermont March 15 th, 15

12 bit resolution 11. 5 bits effective resolution Stefan Ritt DPP Workshop PSI March 15 th, 2011 <8 bits effective resolution 16

Bandwidth is determined by bond wire and internal bus resistance/capacitance: 850 MHz (QFP), 950 MHz (QFN), ? ? ? (flip-chip) ~2 n. H Bond wire Parasitic ~10 p. F final bus width QFP package 850 MHz (-3 d. B) Simulation Measurement Ueli Hartmann Stefan Ritt DPP Workshop PSI March 15 th, 2011 17

Bump Bonding Reduce input inductance by using bump bonding instead of wire bonding 200 mm 75 mm Stefan Ritt DPP Workshop PSI March 15 th, 2011 18

How to minimize dead time ? • Fast analog readout: 30 ns / sample • Parallel readout • Region-of-interest readout • Simultaneous write / read AD 9222 12 bit 8 channels Stefan Ritt DPP Workshop PSI March 15 th, 2011 19

ROI readout mode delayed trigger stop normal trigger stop after latency Trigger Delay stop 33 MHz e. g. 100 samples @ 33 MHz 3 us dead time 300, 000 events / sec. Stefan Ritt readout shift register Patent pending! DPP Workshop PSIClermont March 15 th, 20

Daisy-chaining of channels Domino Wave clock 1 enable input Channel 0 0 enable input Channel 1 1 Channel 2 0 Channel 3 1 Channel 4 0 Channel 5 1 Channel 6 0 Channel 7 1 Channel 7 DRS 4 can be partitioned in: 8 x 1024, 4 x 2048, 2 x 4096, 1 x 8192 cells Chip daisy-chaining possible to reach virtually unlimited sampling depth Stefan Ritt DPP Workshop PSIClermont March 15 th, 21

Simultaneous Write/Read FPGA 0 1 Channel 0 0 1 Channel 1 1 0 Channel 2 0 Channel 3 0 Channel 4 0 Channel 5 0 Channel 6 0 Channel 7 readout 8 -fold analog multi-event buffer Expected crosstalk ~few m. V Stefan Ritt DPP Workshop PSIClermont March 15 th, 22

DRS 4 around the world Shipped (-Jan 2011): 2200 Chips 120 Evaluation Boards Stefan Ritt DPP Workshop PSIClermont March 15 th, 23

MEG Experiment • MEG experiment @ PSI searches for m eg decay • After ~10 years of chip design, DAQ setup, firmware programming, MEG runs with 3000 channels as designed • 40 ps timing resolutions between all channels, running at 1. 6 GS/s • “Double buffer” readout mode increases life time to 99. 7 % at 10 Hz event rate (3 MB/event) • Took 400 TB in 2010 Stefan Ritt DPP Workshop PSIClermont March 15 th, 24

DRS 4 @ MEG LMK 03000 32 channels 4 x DRS 4 3000 Channels Stefan Ritt DPP Workshop PSI March 15 th, 2011 25

On-line waveform display S 848 PMTs “virtual oscilloscope” template fit click pedestal histo Stefan Ritt DPP Workshop PSI March 15 th, 2011 26

Crosstalk elimination Crosstalk removal by subtracting empty channel subtract Hit Stefan Ritt Hit DPP Workshop PSI March 15 th, 2011 27

Template Fit • Determine “standard” PMT pulse by averaging over many events “Template” • Find hit in waveform • Shift (“TDC”) and scale (“ADC”) template to hit • Minimize c 2 • Compare fit with waveform • Repeat if above threshold • Store ADC & TDC values Stefan Ritt DPP Workshop PSI March 15 th, 2011 pb Experiment 500 MHz sampling 28

Trigger and DAQ on same board global trigger bus MUX analog front end • SCA can only sample a limited (1024 -bin window) many application require a wider window, trigger capability would require continuous digitization • Using a multiplexer in DRS 4, input signals can simultaneously digitized at 120 MHz and sampled in the DRS • FPGA can make local trigger (or global one) and stop DRS upon a trigger • DRS readout (5 GSPS) DRS 4 trigger though same 8 -channel FADC DRS 12 bit FPGA 65 MHz FADCs LVDS SRAM Stefan Ritt DPP Workshop PSIClermont March 15 th, 29

“Slow” waveform and “Fast” window Triggered DRS Waveform 1 GSPS (1 ns bins) up to 5 GSPS Continuous Waveform 120 MSPS (8 ns bins) Stefan Ritt Window only limited by RAM DPP Workshop PSIClermont March 15 th, 30

Sine Curve Fit Method i yji : i-th sample of measurement j aj fj aj oj : sine wave parameters bi : phase error fixed jitter “Iterative global fit”: • Determine rough sine wave parameters for each measurement by fit • Determine bi using all measurements where sample “i” is near zero crossing • Make several iterations j Stefan Ritt S. Lehner, B. Keil, PSI DPP Workshop PSI March 15 th, 2011 31

Fixed Pattern Jitter Results • TDi typically ~50 ps RMS @ 5 GHz • TIi goes up to ~600 ps • Jitter is mostly constant over time, measured and corrected • Residual random jitter 3 -4 ps RMS • Achievable resolution exceeds best CFD + HPTDC Stefan Ritt DPP Workshop PSI March 15 th, 2011 32

Time-of-Flight PET • Conventional electronics: CFD – TDC: 500 ps RMS • TOF needs: • 100 -200 ps • >1 MHz rate C. Levin, Stanford University Stefan Ritt DPP Workshop PSIClermont March 15 th, 33

To. F-PET Project • • Started fall 2010 after NSS/MIC in Knoxville (Siemens PET R&D home) New project started to replace current PET electronics with DRS 4 (5) PCB ready summer 2011, firmware by Univ. Tübingen Simulations show that SCA technique can achieve 100 ps easily FPGA Stefan Ritt “Ping-Pong Scheme” 1 Channel 0 0 Channel 1 0 Channel 2 0 Channel 3 0 Channel 4 0 Channel 5 0 Channel 6 0 Channel 7 ROI 20 samples (10 ns @ 2 GS/s) * 30 ns / sample = 600 ns + 40 ns overhead = 640 ns 1 MHz rate DPP Workshop PSIClermont March 15 th, 34

DRS 5 Chip Ideas Stefan Ritt DPP Workshop PSIClermont March 15 th, 35

Plans for DRS 5 • • Increase analog bandwidth ~5 GHz • Smaller input capacitance Increase sampling speed ~10 GS/s • Switch to 110 nm technology Deeper sampling depth • 8 x 4096 / chip Minimize readout time (“dead time free”) for mu. SR & To. F-PET • (minor) reduction in analog readout speed (30 ns 20 ns) • Implement FIFO technology CTA Stefan Ritt J. Milnes, J. Howoth, Photek m. SR ~MHz event rate DPP Workshop PSIClermont March 15 th, 36

Next Generation SCA Short sampling depth Deep sampling depth • Low parasitic input • Digitize long waveforms How to combine capacitance best of both worlds? High bandwidth • Accommodate long • Large area trigger delay low resistance bus, low resistance analog switches • Faster sampling speed high bandwidth for a given trigger latency Stefan Ritt DPP Workshop PSIClermont March 15 th, 37

Cascaded Switched Capacitor Arrays shift register input • 32 fast sampling cells (10 GSPS/110 nm CMOS) • 100 ps sample time, 3. 1 ns hold time • Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz) • Shift register gets clocked by inverter chain from fast sampling stage . . . . fast sampling stage Stefan Ritt secondary sampling stage DPP Workshop PSIClermont March 15 th, 38

How noise affects timing voltage noise band of signal voltage noise Du timing jitter arising from voltage noise signal height U timing uncertainty Dt rise time tr timing jitter is much smaller for faster rise-time number of samples on slope Stefan Ritt DPP Workshop PSI March 15 th, 2011 39

TDC vs. Waveform Digitizing PMT/APD Wire Q-sensitive Preamplifier Shaper Constant Fraction Discriminator TDC • CFD and TDC on same board crosstalk • CFD depends on noise on single point, while waveform digitizing can average over several points • Inverter chain is same both in TDCs and SCAs • Can we replace TDCs by SCAs? yes if the readout rate is sufficient Stefan Ritt DPP Workshop PSI March 15 th, 2011 40

Typical Waveform Only short segments of waveform need high speed readout Stefan Ritt DPP Workshop PSIClermont March 15 th, 41

Dead-time free acquisition • • Self-trigger writing of short 32 -bin segments Simultaneous reading of segments Quasi dead time-free Data driven readout • Ext. ADC runs continuously • ASIC tells FPGA when there is new data Coarse timing from 300 MHz counter Fine timing by waveform 5 S digitizing and analysis in FPGA R D 20 * 20 ns = 0. 4 ms readout time 2 MHz sustained event rate Attractive replacement for CFD+TDC Stefan Ritt DPP Workshop PSIClermont March 15 th, 42

Plug & Play Firmware • Emphasis shift from dedicated hardware to firmware • Pre-designed modules for CFD, TDC, peak sensing ADC, … • Modules can be configured by user and downloaded TDC CFD ADC Readout Data bus SCALER FIFO ADC FIFO Interface FIFO Parameter bus Stefan Ritt DPP Workshop PSIClermont March 15 th, 43

Conclusions • DRS 4 chip successfully used in many areas, true potential of SCA technology is just now discovered • Planned DRS 5 chip will increase BW and decrease readout dead time • SCA technology should be able to replace most traditional electronics in particle detection Stefan Ritt DPP Workshop PSIClermont March 15 th, 44

Thanks to … • Roland Horisberger: Original Idea • Roberto Dinapoli: Analog Design of DRS 3+4 • Ueli Hartmann: DRS 4 Evaluation Boards • PSI chip design core team Stefan Ritt DPP Workshop PSI March 15 th, 2011 45