Introduction to CMOS VLSI Design Sequential Circuits Sequential

Introduction to CMOS VLSI Design Sequential Circuits Sequential Logic 1

Outline q q q Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking Sequential Logic CMOS VLSI Design 2

Sequencing q Combinational logic – output depends on current inputs q Sequential logic – output depends on current and previous inputs – Requires separating previous, current, future – Called state or tokens – Ex: FSM, pipeline Sequential Logic CMOS VLSI Design 3

Sequencing Cont. q If tokens moved through pipeline at constant speed, no sequencing elements would be necessary q Ex: fiber-optic cable – Light pulses (tokens) are sent down cable – Next pulse sent before first reaches end of cable – No need for hardware to separate pulses – But dispersion sets min time between pulses q This is called wave pipelining in circuits q In most circuits, dispersion is high – Delay fast tokens so they don’t catch slow ones. Sequential Logic CMOS VLSI Design 4

Sequencing Overhead q Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. q Inevitably adds some delay to the slow tokens q Makes circuit slower than just the logic delay – Called sequencing overhead q Some people call this clocking overhead – But it applies to asynchronous circuits too – Inevitable side effect of maintaining sequence Sequential Logic CMOS VLSI Design 5

Sequencing Elements q Latch: Level sensitive – a. k. a. transparent latch, D latch q Flip-flop: edge triggered – A. k. a. master-slave flip-flop, D register q Timing Diagrams – Transparent – Opaque – Edge-trigger Sequential Logic CMOS VLSI Design 6

Sequencing Elements q Latch: Level sensitive – a. k. a. transparent latch, D latch q Flip-flop: edge triggered – A. k. a. master-slave flip-flop, D register q Timing Diagrams – Transparent – Opaque – Edge-trigger Sequential Logic CMOS VLSI Design 7

Latch Design q Pass Transistor Latch q Pros + + q Cons – – – Sequential Logic CMOS VLSI Design 8

Latch Design q Pass Transistor Latch q Pros + Tiny + Low clock load q Cons – Vt drop – nonrestoring – backdriving – output noise sensitivity – dynamic – diffusion input Sequential Logic CMOS VLSI Design Used in 1970’s 9

Latch Design q Transmission gate + - Sequential Logic CMOS VLSI Design 10

Latch Design q Transmission gate + No Vt drop - Requires inverted clock Sequential Logic CMOS VLSI Design 11

Latch Design q Inverting buffer + + + Fixes either • • – Sequential Logic CMOS VLSI Design 12

Latch Design q Inverting buffer + Restoring + No backdriving + Fixes either • Output noise sensitivity • Or diffusion input – Inverted output Sequential Logic CMOS VLSI Design 13

Latch Design q Tristate feedback + – Sequential Logic CMOS VLSI Design 14

Latch Design q Tristate feedback + Static – Backdriving risk q Static latches are now essential Sequential Logic CMOS VLSI Design 15

Latch Design q Buffered input + + Sequential Logic CMOS VLSI Design 16

Latch Design q Buffered input + Fixes diffusion input + Noninverting Sequential Logic CMOS VLSI Design 17

Latch Design q Buffered output + Sequential Logic CMOS VLSI Design 18

Latch Design q Buffered output + No backdriving q Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1. 5 – 2 FO 4 delays) - High clock loading Sequential Logic CMOS VLSI Design 19

Latch Design q Datapath latch + - Sequential Logic CMOS VLSI Design 20

Latch Design q Datapath latch + Smaller, faster - unbuffered input Sequential Logic CMOS VLSI Design 21

Flip-Flop Design q Flip-flop is built as pair of back-to-back latches Sequential Logic CMOS VLSI Design 22

Enable q Enable: ignore clock when en = 0 – Mux: increase latch D-Q delay – Clock Gating: increase en setup time, skew Sequential Logic CMOS VLSI Design 23

Reset q Force output low when reset asserted q Synchronous vs. asynchronous Sequential Logic CMOS VLSI Design 24

Set / Reset q Set forces output high when enabled q Flip-flop with asynchronous set and reset Sequential Logic CMOS VLSI Design 25

Sequencing Methods q Flip-flops q 2 -Phase Latches q Pulsed Latches Sequential Logic CMOS VLSI Design 26

Timing Diagrams Contamination and Propagation Delays tpd Logic Prop. Delay tcd Logic Cont. Delay tpcq Latch/Flop Clk-Q Prop Delay tccq Latch/Flop Clk-Q Cont. Delay tpdq Latch D-Q Prop Delay tpcq Latch D-Q Cont. Delay tsetup Latch/Flop Setup Time thold Latch/Flop Hold Time Sequential Logic CMOS VLSI Design 27

Max-Delay: Flip-Flops Sequential Logic CMOS VLSI Design 28

Max-Delay: Flip-Flops Sequential Logic CMOS VLSI Design 29

Max Delay: 2 -Phase Latches Sequential Logic CMOS VLSI Design 30

Max Delay: 2 -Phase Latches Sequential Logic CMOS VLSI Design 31

Max Delay: Pulsed Latches Sequential Logic CMOS VLSI Design 32

Max Delay: Pulsed Latches Sequential Logic CMOS VLSI Design 33

Min-Delay: Flip-Flops Sequential Logic CMOS VLSI Design 34

Min-Delay: Flip-Flops Sequential Logic CMOS VLSI Design 35

Min-Delay: 2 -Phase Latches Hold time reduced by nonoverlap Sequential Logic CMOS VLSI Design 36

Min-Delay: 2 -Phase Latches Hold time reduced by nonoverlap Sequential Logic CMOS VLSI Design 37

Min-Delay: Pulsed Latches Hold time increased by pulse width Sequential Logic CMOS VLSI Design 38

Min-Delay: Pulsed Latches Hold time increased by pulse width Sequential Logic CMOS VLSI Design 39

Time Borrowing q In a flop-based system: – Data launches on one rising edge – Must setup before next rising edge – If it arrives late, system fails – If it arrives early, time is wasted – Flops have hard edges q In a latch-based system – Data can pass through latch while transparent – Long cycle of logic can borrow time into next – As long as each loop completes in one cycle Sequential Logic CMOS VLSI Design 40

Time Borrowing Example Sequential Logic CMOS VLSI Design 41

How Much Borrowing? 2 -Phase Latches Pulsed Latches Sequential Logic CMOS VLSI Design 42

Clock Skew q We have assumed zero clock skew q Clocks really have uncertainty in arrival time – Decreases maximum propagation delay – Increases minimum contamination delay – Decreases time borrowing Sequential Logic CMOS VLSI Design 43

Skew: Flip-Flops Sequential Logic CMOS VLSI Design 44

Skew: Latches 2 -Phase Latches Pulsed Latches Sequential Logic CMOS VLSI Design 45

Two-Phase Clocking q If setup times are violated, reduce clock speed q If hold times are violated, chip fails at any speed q Working chips are most important – Analyzing clock skew difficult q An easy way to guarantee hold times is to use 2 phase latches with big nonoverlap times q Call these clocks f 1, f 2 (ph 1, ph 2) Sequential Logic CMOS VLSI Design 46

Safe Flip-Flop q In class, use flip-flop with nonoverlapping clocks – Very slow – nonoverlap adds to setup time – But no hold times q In industry, use a better timing analyzer – Add buffers to slow signals if hold time is at risk Sequential Logic CMOS VLSI Design 47

Summary q Flip-Flops: – Very easy to use, supported by all tools q 2 -Phase Transparent Latches: – Lots of skew tolerance and time borrowing q Pulsed Latches: – Fast, some skew tol & borrow, hold time risk Sequential Logic CMOS VLSI Design 48