Introduction to CMOS VLSI Design Combinational Circuits 1

Outline q q q q Bubble Pushing Compound Gates Logical Effort Example Input Ordering Asymmetric Gates Skewed Gates Best P/N ratio Combinational Circuits CMOS VLSI Design 2

Example 1 module mux(input s, d 0, d 1, output y); assign y = s ? d 1 : d 0; endmodule 1) Sketch a design using AND, OR, and NOT gates. Combinational Circuits CMOS VLSI Design 3

Example 1 module mux(input s, d 0, d 1, output y); assign y = s ? d 1 : d 0; endmodule 1) Sketch a design using AND, OR, and NOT gates. Combinational Circuits CMOS VLSI Design 4

Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. Combinational Circuits CMOS VLSI Design 5

Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. Combinational Circuits CMOS VLSI Design 6

Bubble Pushing q Start with network of AND / OR gates q Convert to NAND / NOR + inverters q Push bubbles around to simplify logic – Remember De. Morgan’s Law Combinational Circuits CMOS VLSI Design 7

Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. Combinational Circuits CMOS VLSI Design 8

Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. Combinational Circuits CMOS VLSI Design 9

Compound Gates q Logical Effort of compound gates Combinational Circuits CMOS VLSI Design 10

Inner & Outer Inputs q Outer input is closest to rail (B) q Inner input is closest to output (A) q If input arrival time is known – Connect latest input to inner terminal Combinational Circuits CMOS VLSI Design 22

Asymmetric Gates q Asymmetric gates favor one input over another q Ex: suppose input A of a NAND gate is most critical – Use smaller transistor on A (less capacitance) – Boost size of noncritical input – So total resistance is same q g. A = q g. B = q gtotal = g. A + g. B = q Asymmetric gate approaches g = 1 on critical input q But total logical effort goes up Combinational Circuits CMOS VLSI Design 23

Asymmetric Gates q Asymmetric gates favor one input over another q Ex: suppose input A of a NAND gate is most critical – Use smaller transistor on A (less capacitance) – Boost size of noncritical input – So total resistance is same q g. A = 10/9 q g. B = 2 q gtotal = g. A + g. B = 28/9 q Asymmetric gate approaches g = 1 on critical input q But total logical effort goes up Combinational Circuits CMOS VLSI Design 24

Symmetric Gates q Inputs can be made perfectly symmetric Combinational Circuits CMOS VLSI Design 25

Skewed Gates q Skewed gates favor one edge over another q Ex: suppose rising output of inverter is most critical – Downsize noncritical n. MOS transistor q Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. – gu = – gd = Combinational Circuits CMOS VLSI Design 26

Skewed Gates q Skewed gates favor one edge over another q Ex: suppose rising output of inverter is most critical – Downsize noncritical n. MOS transistor q Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. – gu = 2. 5 / 3 = 5/6 – gd = 2. 5 / 1. 5 = 5/3 Combinational Circuits CMOS VLSI Design 27

HI- and LO-Skew q Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. q Skewed gates reduce size of noncritical transistors – HI-skew gates favor rising output (small n. MOS) – LO-skew gates favor falling output (small p. MOS) q Logical effort is smaller for favored direction q But larger for the other direction Combinational Circuits CMOS VLSI Design 28

Catalog of Skewed Gates Combinational Circuits CMOS VLSI Design 29

Catalog of Skewed Gates Combinational Circuits CMOS VLSI Design 30

Catalog of Skewed Gates Combinational Circuits CMOS VLSI Design 31

Asymmetric Skew q Combine asymmetric and skewed gates – Downsize noncritical transistor on unimportant input – Reduces parasitic delay for critical input Combinational Circuits CMOS VLSI Design 32

Best P/N Ratio q We have selected P/N ratio for unit rise and fall resistance (m = 2 -3 for an inverter). q Alternative: choose ratio for least average delay q Ex: inverter – Delay driving identical inverter – tpdf = – tpdr = – tpd = – Differentiate tpd w. r. t. P – Least delay for P = Combinational Circuits CMOS VLSI Design 33

Best P/N Ratio q We have selected P/N ratio for unit rise and fall resistance (m = 2 -3 for an inverter). q Alternative: choose ratio for least average delay q Ex: inverter – Delay driving identical inverter – tpdf = (P+1) – tpdr = (P+1)(m/P) – tpd = (P+1)(1+m/P)/2 = (P + 1 + m/P)/2 – Differentiate tpd w. r. t. P – Least delay for P = Combinational Circuits CMOS VLSI Design 34

P/N Ratios q In general, best P/N ratio is sqrt of equal delay ratio. – Only improves average delay slightly for inverters – But significantly decreases area and power Combinational Circuits CMOS VLSI Design 35

P/N Ratios q In general, best P/N ratio is sqrt of that giving equal delay. – Only improves average delay slightly for inverters – But significantly decreases area and power Combinational Circuits CMOS VLSI Design 36

Observations q For speed: – NAND vs. NOR – Many simple stages vs. fewer high fan-in stages – Latest-arriving input q For area and power: – Many simple stages vs. fewer high fan-in stages Combinational Circuits CMOS VLSI Design 37