Introduction to CMOS VLSI Design Lecture 5 CMOS

Introduction to CMOS VLSI Design Lecture 5 CMOS Transistor Theory Manoel E. de Lima David Harris Harvey Mudd College

Outline q q q q Introduction MOS Capacitor n. MOS I-V Characteristics p. MOS I-V Characteristics Gate and Diffusion Capacitance Pass Transistors RC Delay Models 3: CMOS Transistor Theory CMOS VLSI Design Slide 2

Introduction q So far, we have treated transistors as ideal switches q An ON transistor passes a finite amount of current – Depends on terminal voltages – Derive current-voltage (I-V) relationships q Transistor gate, source, drain all have capacitance – I = C (DV/Dt) -> Dt = (C/I) DV – Capacitance and current determine speed q Also explore what a “degraded level” really means 3: CMOS Transistor Theory CMOS VLSI Design Slide 3

MOS Capacitor q Gate and body form MOS capacitor q Operating modes – Accumulation – Depletion – Inversion 3: CMOS Transistor Theory CMOS VLSI Design Slide 4

Terminal Voltages q Mode of operation depends on Vg, Vd, Vs – Vgs = Vg – Vs – Vgd = Vg – Vds = Vd – Vs = Vgd - Vgs q Source and drain are symmetric diffusion terminals – By convention, source is terminal at lower voltage – Hence Vds 0 q n. MOS body is grounded. First assume source is 0 too. q Three regions of operation – Cutoff – Linear – Saturation 3: CMOS Transistor Theory CMOS VLSI Design Slide 5

n. MOS Cutoff q No channel q Ids = 0 q Vgs ≤ 0 3: CMOS Transistor Theory CMOS VLSI Design Slide 6

n. MOS Linear q Channel forms q Current flows from d to s – e- from s to d q Ids increases with Vds q Similar to linear resistor 3: CMOS Transistor Theory CMOS VLSI Design Slide 7

I-V Characteristics q In Linear region, Ids depends on – How much charge is in the channel? – How fast is the charge moving? 3: CMOS Transistor Theory CMOS VLSI Design Slide 8

Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel 3: CMOS Transistor Theory CMOS VLSI Design Slide 9

Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel q Qchannel = CV Cox = eox / tox q C = Cg = eox. WL/tox = Cox. WL q V = Vgc – Vt = (Vgs – Vds/2) – Vt 3: CMOS Transistor Theory CMOS VLSI Design Slide 10

Carrier velocity q Charge is carried by eq Carrier velocity v proportional to lateral E-field between source and drain q v= 3: CMOS Transistor Theory CMOS VLSI Design Slide 11

Carrier velocity q Charge is carried by eq Carrier velocity v proportional to lateral E-field between source and drain q v = m. E m called mobility q E= 3: CMOS Transistor Theory CMOS VLSI Design Slide 12

Carrier velocity q Charge is carried by eq Carrier velocity v proportional to lateral E-field between source and drain q v = m. E m called mobility q E = Vds/L q Time for carrier to cross channel: – t= 3: CMOS Transistor Theory CMOS VLSI Design Slide 13

Carrier velocity q Charge is carried by eq Carrier velocity v proportional to lateral E-field between source and drain q v = m. E m called mobility q E = Vds/L q Time for carrier to cross channel: – t=L/v 3: CMOS Transistor Theory CMOS VLSI Design Slide 14

n. MOS Linear I-V q Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross Cox= oxide capacitance = β (Vgs-Vt )Vds -Vds 2/2 = β (Vgs-Vt )Vds It is a region called linear region. Here Ids varies linearly, with Vgs and Vds when the quadratic term Vds 2/2 is very small. Vds << Vgs-Vt 3: CMOS Transistor Theory CMOS VLSI Design Slide 15

n. MOS Saturation q q Channel pinches off Ids independent of Vds We say current saturates Similar to current source 3: CMOS Transistor Theory CMOS VLSI Design Slide 16

n. MOS Saturation I-V q If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt q Now drain voltage no longer increases current = β (Vgs-Vt )Vds -Vds 2/2 Where 0 < Vgs – Vt <Vds, considering (Vgs-Vt )=Vds we have Ids = β (Vgs-Vt ) 2/2 3: CMOS Transistor Theory CMOS VLSI Design Slide 17

n. MOS I-V Summary q n. MOS Characteristics 3: CMOS Transistor Theory CMOS VLSI Design Slide 18

Example q We will be using a 0. 6 mm process for your project – From AMI Semiconductor – tox = 100 Å – m = 350 cm 2/V*s – Vt = 0. 7 V q Plot Ids vs. Vds – Vgs = 0, 1, 2, 3, 4, 5 – Use W/L = 4/2 l 3: CMOS Transistor Theory CMOS VLSI Design Slide 19

p. MOS I-V q All dopings and voltages are inverted for p. MOS q Mobility mp is determined by holes – Typically 2 -3 x lower than that of electrons mn – 120 cm 2/V*s in AMI 0. 6 mm process q Thus p. MOS must be wider to provide same current – In this class, assume mn / mp = 2 3: CMOS Transistor Theory CMOS VLSI Design Slide 20

Capacitance q Any two conductors separated by an insulator have capacitance q Gate to channel capacitor is very important – Creates channel charge necessary for operation q Source and drain have capacitance to body – Across reverse-biased diodes – Called diffusion capacitance because it is associated with source/drain diffusion 3: CMOS Transistor Theory CMOS VLSI Design Slide 21

Gate Capacitance q Approximate channel as connected to source q Cgs = eox. WL/tox = Cox. WL = Cpermicron. W q Cpermicron is typically about 2 f. F/mm 3: CMOS Transistor Theory CMOS VLSI Design Slide 22

Diffusion Capacitance q Csb, Cdb q Undesirable, called parasitic capacitance q Capacitance depends on area and perimeter – Use small diffusion nodes – Varies with process 3: CMOS Transistor Theory CMOS VLSI Design Slide 23

Pass Transistors q We have assumed source is grounded q What if source > 0? – e. g. pass transistor passing VDD 3: CMOS Transistor Theory CMOS VLSI Design Slide 24

Pass Transistors q We have assumed source is grounded q What if source > 0? – e. g. pass transistor passing VDD q Vg = VDD – If Vs > VDD-Vt, Vgs < Vt – Hence transistor would turn itself off q n. MOS pass transistors pull no higher than VDD-Vtn – Called a degraded “ 1” – Approach degraded value slowly (low Ids) q p. MOS pass transistors pull no lower than Vtp 3: CMOS Transistor Theory CMOS VLSI Design Slide 25

Pass Transistor 3: CMOS Transistor Theory CMOS VLSI Design Slide 26

Pass Transistor Ckts 3: CMOS Transistor Theory CMOS VLSI Design Slide 27

Effective Resistance q Shockley models have limited value – Not accurate enough for modern transistors – Too complicated for much hand analysis q Simplification: treat transistor as resistor – Replace Ids(Vds, Vgs) with effective resistance R • Ids = Vds/R – R averaged across switching of digital gate q Too inaccurate to predict current at any given time – But good enough to predict RC delay 3: CMOS Transistor Theory CMOS VLSI Design Slide 28

RC Delay Model q Use equivalent circuits for MOS transistors – Ideal switch + capacitance and ON resistance – Unit n. MOS has resistance R, capacitance C – Unit p. MOS has resistance 2 R, capacitance C q Capacitance proportional to width q Resistance inversely proportional to width 3: CMOS Transistor Theory CMOS VLSI Design Slide 29

RC Values q Capacitance – C = Cg = Cs = Cd = 2 f. F/mm of gate width – Values similar across many processes q Resistance – R 6 K *mm in 0. 6 um process – Improves with shorter channel lengths q Unit transistors – May refer to minimum contacted device (4/2 l) – Or maybe 1 mm wide device – Doesn’t matter as long as you are consistent 3: CMOS Transistor Theory CMOS VLSI Design Slide 30

Inverter Delay Estimate q Estimate the delay of a fanout-of-1 inverter R in p. MOS is divided by 2 since its width is the double of the n. MOS 3: CMOS Transistor Theory CMOS VLSI Design Slide 31

Inverter Delay Estimate q Estimate the delay of a fanout-of-1 inverter 3: CMOS Transistor Theory CMOS VLSI Design Slide 32

Inverter Delay Estimate q Estimate the delay of a fanout-of-1 inverter 3: CMOS Transistor Theory CMOS VLSI Design Slide 33

Inverter Delay Estimate q Estimate the delay of a fanout-of-1 inverter d = 6 RC 3: CMOS Transistor Theory CMOS VLSI Design Slide 34

+5 V R In Vil=0 Roff 1010 X Out Iih Ioh Voh(min) Vih(min) GND Transistor não conduz Capacitor Tensão(V) Vih(min) Nível ´ 1´ Tempo (seg) CMOS VLSI Design

+5 V R In Vih=´ 1´ Vol(max) Ron 1 K Out Iil Iol Vil(max) GND Transistor conduz Capacitor inicialmente carregado = “ 1” Tensão(V) Nível ´ 0´ Vil(max) Tempo (seg) CMOS VLSI Design