Figure 5 1 An example of ANDOR logic

Figure 5. 2 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 3 An AND-OR-Invert circuit produces a POS output. Open file F 05

Figure 5. 4 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 5 Exclusive-OR logic diagram and symbols. Open file F 05 -05 to

Figure 5. 6 Two equivalent ways of implementing the exclusive-NOR. Open files F 05

Figure 5. 7 Even-parity generator. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright ©

Figure 5. 8 Even-parity checker. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright ©

Figure 5. 9 Logic circuit for X = AB + CDE. Digital Fundamentals, Tenth

_ _ Figure 5. 10 Logic circuits for X = AB(CD + EF) =

_ __ Figure 5. 11 Logic circuit for Open file F 05 -11 to

Figure 5. 12 Open file F 05 -12 to verify the operation. Digital Fundamentals,

Figure 5. 13 Open file F 05 -13 to verify the operation. Digital Fundamentals,

Figure 5. 14 Open file F 05 -14 to verify that this circuit is

Figure 5. 15 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 16 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 17 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 18 Universal application of NAND gates. Open files F 05 -18(a), (b),

Figure 5. 19 Universal application of NOR gates. Open files F 05 -19(a), (b),

Figure 5. 20 NAND logic for X = AB + CD. Digital Fundamentals, Tenth

Figure 5. 21 Development of the AND-OR equivalent of the circuit in Figure 5–

Figure 5. 22 Illustration of the use of the appropriate dual symbols in a

Figure 5. 23 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 24 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 25 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 26 NOR logic for X = (A + B)(C + D). Digital

Figure 5. 27 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 28 Illustration of the use of the appropriate dual symbols in a

Figure 5. 29 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 30 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 31 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 32 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 33 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 34 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 35 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 36 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 37 Illustration of a node in a logic circuit. Digital Fundamentals, Tenth

Figure 5. 38 Open output in driving gate. Assume a HIGH is on one

Figure 5. 39 Open input in a load gate. Digital Fundamentals, Tenth Edition Thomas

Figure 5. 40 Shorted output in the driving gate or shorted input in a

Figure 5. 41 Example of signal tracing and waveform analysis in a portion of

Figure 5. 42 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 43 Simplified comparison of the VHDL structural approach to a hardware implementation.

Figure 5. 44 Predefined programs for a 2 -input AND gate and a 2

Figure 5. 45 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 46 Illustration of the instantiation statements and port mapping applied to the

Figure 5. 47 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 48 A VHDL program for a combinational logic circuit after entry on

Figure 5. 49 A typical waveform editor tool showing the simulated waveforms for the

Figure 5. 50 Tank with level and temperature sensors and controls. Digital Fundamentals, Tenth

Figure 5. 51 Multisim circuit screen for the valve control logic. Digital Fundamentals, Tenth

Figure 5. 52 Block diagram for temperature control circuit. Digital Fundamentals, Tenth Edition Thomas

Figure 5. 53 Logic diagram of the temperature control logic. Digital Fundamentals, Tenth Edition

Figure 5. 54 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 55 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 56 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 57 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 58 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 59 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 60 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 61 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 62 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 63 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 64 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 65 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 66 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 67 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 68 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 69 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 70 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 71 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 72 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 73 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 74 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 75 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 76 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 77 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 78 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 5. 79 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

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Figure 5. 1 An example of AND-OR logic. Open file F 05 -01 to verify the operation. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 3 An AND-OR-Invert circuit produces a POS output. Open file F 05 -03 to verify the operation. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 5 Exclusive-OR logic diagram and symbols. Open file F 05 -05 to verify the operation. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 6 Two equivalent ways of implementing the exclusive-NOR. Open files F 05 -06 (a) and (b) to verify the operation. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 9 Logic circuit for X = AB + CDE. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

_ _ Figure 5. 10 Logic circuits for X = AB(CD + EF) = ABCD + ABEF. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

_ __ Figure 5. 11 Logic circuit for Open file F 05 -11 to verify the operation. X = ABC + ABC. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 12 Open file F 05 -12 to verify the operation. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 13 Open file F 05 -13 to verify the operation. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 14 Open file F 05 -14 to verify that this circuit is equivalent to the circuit in Figure 5– 15. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 18 Universal application of NAND gates. Open files F 05 -18(a), (b), (c), and (d) to verify each of the equivalencies. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 19 Universal application of NOR gates. Open files F 05 -19(a), (b), (c), and (d) to verify each of the equivalencies. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 20 NAND logic for X = AB + CD. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 21 Development of the AND-OR equivalent of the circuit in Figure 5– 20. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 22 Illustration of the use of the appropriate dual symbols in a NAND logic diagram. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 26 NOR logic for X = (A + B)(C + D). Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 28 Illustration of the use of the appropriate dual symbols in a NOR logic diagram. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 37 Illustration of a node in a logic circuit. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 38 Open output in driving gate. Assume a HIGH is on one gate input. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 40 Shorted output in the driving gate or shorted input in a load gate. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 41 Example of signal tracing and waveform analysis in a portion of a printed circuit board. TP indicates test point. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 43 Simplified comparison of the VHDL structural approach to a hardware implementation. The VHDL signals correspond to the interconnections on the circuit board, and the VHDL components correspond to the IC devices. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 44 Predefined programs for a 2 -input AND gate and a 2 -input OR gate to be used as components in the data flow approach. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 46 Illustration of the instantiation statements and port mapping applied to the AND-OR logic. Signals are shown in red. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 48 A VHDL program for a combinational logic circuit after entry on a generic text editor screen that is part of a software development tool. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 49 A typical waveform editor tool showing the simulated waveforms for the logic circuit described by the VHDL code in Figure 5– 48. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 50 Tank with level and temperature sensors and controls. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 51 Multisim circuit screen for the valve control logic. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 52 Block diagram for temperature control circuit. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 5. 53 Logic diagram of the temperature control logic. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.