Week 14 a Propagation delay of logic gates

Week 14 a Propagation delay of logic gates CMOS (complementary MOS) logic gates Pull-down and pull-up The basic CMOS inverter Current flow and power dissipation in CMOS circuits Equation for power dissipated in N logic circuits clocked at frequency f EE 42/100, Spring 2006 Week 14 a, Prof. White 1

WHAT IS THE ORIGIN OF GATE DELAY? Logic gates are electronic circuits that process electrical signals Most common signal for logic variable: voltage Specific voltage ranges correspond to “ 0” or “ 1” Thus delay in voltage rise or fall (because of delay in charging internal capacitances) will translate to a delay in signal timing Note that the specific voltage range for 0 or 1 depends on “logic family, ” and in general decreases with succeeding logic generations EE 42/100, Spring 2006 Week 14 a, Prof. White 2

INVERTER VOLTAGE WAVEFORMS (TIME FUNCTIONS) Inverter input is v. IN(t), output is v. OUT(t) Inverter inside a large system Vin(t) t EE 42/100, Spring 2006 Week 14 a, Prof. White 3

GATE DELAY (PROPAGATION DELAY) Define as the delay required for the output voltage to reach 50% of its final value. In this example we will use 3 V logic, so halfway point is 1. 5 V. Inverters are designed so that the gate delay is symmetrical (rise and fall) Vin(t) 1. 5 t Vout(t) Approximation 1. 5 EE 42/100, Spring 2006 D Week DWhite D 14 a, Prof. t 4

EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEED Computer architects would like each system clock cycle to have between 20 and 50 gate delays … use 35 for calculations Implication: if clock frequency = 500 MHz clock period = (5 108 s 1) 1 Period = 2 10 9 s = 2 ns (nanoseconds) Gate delay must be D = (1/35) Period = (2 ns)/35 = 57 ps (picoseconds) How fast is this? Speed of light: c = 3 108 m/s Distance traveled in 57 ps is: c. X D = (3 x 108 m/s)(57 x 10 -12 s) = 17 x 10 -4 m = 1. 7 cm EE 42/100, Spring 2006 Week 14 a, Prof. White 5

WHAT DETERMINES GATE DELAY? The delay is mostly simply the charging of the capacitors at internal nodes. Logic gates consist of just “CMOS” transistor circuits (CMOS = complementary metal-oxide-semiconductor = NMOS and PMOS FETs together). Let’s recall the FET EE 42/100, Spring 2006 Week 14 a, Prof. White 6

Modern Field Effect Transistor (FET) • An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying “gate” electrode), to modulate the conductance of the semiconductor ® Modulate drift current flowing between 2 contacts (“source” and “drain”) by varying the voltage on the “gate” electrode N-channel metal-oxidesemiconductor field-effect transistor (NMOSFET) EE 42/100, Spring 2006 Week 14 a, Prof. White 7

Pull-Down and Pull-Up Devices • In CMOS logic gates, NMOSFETs are used to connect the output to GND, whereas PMOSFETs are used to connect the output to VDD. – An NMOSFET functions as a pull-down device when it is turned on (gate voltage = VDD) – A PMOSFET functions as a pull-up device when it is turned on (gate voltage = GND) VDD EE 42/100, Spring 2006 Pull-up network PMOSFETs only F(A 1, A 2, …, AN) … A 1 A 2 AN … input signals A 1 A 2 AN Pull-down network Week 14 a, Prof. White NMOSFETs only 8

Controlled Switch Model G Input + - - RN + Output +- S G Input + - - RP + Output +- Type N controlled switch” means switch is closed if input is high. (VG > VS) Type P controlled switch” means switch is closed if input is low. (VG < VS) S Now lets combine these switches to make an inverter. EE 42/100, Spring 2006 Week 14 a, Prof. White 9

The CMOS Inverter: Current Flow during Switching N: sat P: sat VOUT V DD N: off P: lin VDD S G i VOUT A D G C N: sat P: lin D V IN i B E N: lin P: sat S N: lin P: off 0 0 EE 42/100, Spring 2006 D Week 14 a, Prof. White VDD VIN 10

CMOS Inverter Power Dissipation due to Direct. Path Current VDD VDD-VT v. IN: S G D i v. IN 0 Ipeak v. OUT D G S VT i: 0 tsc time Note: once the CMOS circuit reaches a steady state there’s no more current flow and hence no more power dissipation! Energy consumed per switching period: EE 42/100, Spring 2006 Week 14 a, Prof. White 11

Controlled Switch Model of Inverter VDD = 2 V SP is closed if VIN < VDD RP VIN + - SP + RN Input VOUT + +SN is closed if Output VIN > VSS SN - VSS = 0 V So if VIN is 2 V then SN is closed and SP is open. Hence VOUT is zero. But if VIN is 0 V then SP is closed and SN is open. Hence VOUT is 2 V. EE 42/100, Spring 2006 Week 14 a, Prof. White 12

Controlled Switch Model of Inverter VDD = 2 V VIN =2 V RN - SS = 0 V V + VOUT - IF VIN is 2 V then SN is closed and SP is open. Hence VOUT is zero (but driven through resistance RN). VDD = 2 V VIN =0 V RP + VOUT - SS = 0 V V EE 42/100, Spring 2006 - But if VIN is 0 V then SP is closed and SN is open. Hence VOUT is 2 V (but driven through resistance RP). Week 14 a, Prof. White 13

Controlled Switch Model of Inverter – load capacitor charging and discharging takes time VDD = 2 V VIN =2 V RN - SS = 0 V V + VOUT - IF there is a capacitance at the output node (there always is) then VOUT responds to a change in VIN with our usual exponential form. VOUT VDD = 2 V VIN =0 V VIN jumps from 2 V to 0 V RP + VOUT - SS = 0 V V EE 42/100, Spring 2006 - Week 14 a, Prof. White VIN jumps from 0 V to 2 V t 14

Calculating the Propagation Delay Model the MOSFET in the ON state as a resistive switch: Case 1: Vout changing from High to Low (input signal changed from Low to High) § NMOSFET(s) connect Vout to GND VDD tp. HL= 0. 69 Rn. CL Pull-up network is modeled as an open switch v. IN = VDD Pull-down network is modeled as a resistor Rn + CL v. OUT EE 42/100, Spring 2006 Week 14 a, Prof. White 15

Calculating the Propagation Delay (cont’d) Case 2: Vout changing from Low to High (input signal changed from High to Low) § PMOSFET(s) connect Vout to VDD tp. LH = 0. 69 Rp. CL Pull-up network is modeled as a resistor Rp v. IN = 0 V Pull-down network is modeled as an open switch + CL v. OUT EE 42/100, Spring 2006 Week 14 a, Prof. White 16

Output Capacitance of a Logic Gate • The output capacitance of a logic gate is comprised of several components: “intrinsic • capacitance” pn-junction and gate-drain capacitance – both NMOS and PMOS transistors • capacitance of connecting wires “extrinsic capacitance” • input capacitances of the fan-out gates EE 42/100, Spring 2006 Week 14 a, Prof. White 17

Reminder: Fan-Out • Typically, the output of a logic gate is connected to the input(s) of one or more logic gates • The fan-out is the number of gates that are connected to the output of the driving gate: 1 2 driving gate N • • • fan-out =N • Fanout leads to increased capacitive load on the driving gate, and therefore more propagation delay – The input capacitances of the driven gates sum, and must be charged through the equivalent resistance of the driver EE 42/100, Spring 2006 Week 14 a, Prof. White 18

Minimizing Propagation Delay • A fast gate is built by 1. Keeping the output capacitance CL small – Minimize the area of drain pn junctions. – Lay out devices to minimize interconnect capacitance. – Avoid large fan-out. 2. Decreasing the equivalent resistance of the transistors – Decrease L (gate length source to drain) – Increase W (other dimension of gate) … but this increases pn junction area and hence CL 3. Increasing VDD → trade-off with power consumption & reliability EE 42/100, Spring 2006 Week 14 a, Prof. White 19

MOSFET • NMOS: N-channel Metal Oxide Semiconductor • L = channel length W • W = channel width GATE L lator “Metal” (heavily doped poly-Si) su oxide in n con ili p-type s n DRAIN SOURCE • A GATE electrode is placed above (electrically insulated from) the silicon surface, and is used to control the resistance between the SOURCE and DRAIN regions EE 42/100, Spring 2006 Week 14 a, Prof. White 20

Transistor Sizing for Performance VDD G S D VOUT VIN D G S EE 42/100, Spring 2006 • Widening the transistors reduces resistance – current paths in parallel -- but increases gate capacitance • In order to have the on-state resistance of the PMOS transistor match that of the NMOS transistor (e. g. to achieve a symmetric voltage transfer curve), its W/L ratio must be larger by a factor of ~3 (because holes move about 3 times slower than electrons in a given electric field). Week 14 a, Prof. White 21

Other CMOS logic examples EE 42/100, Spring 2006 Week 14 a, Prof. White 22

VDD A CMOS NAND Gate A B 0 0 0 1 1 B F 1 1 1 0 F A B EE 42/100, Spring 2006 Week 14 a, Prof. White 23

VDD CMOS NOR Gate A B 0 0 0 1 1 A F 1 0 0 0 B F B EE 42/100, Spring 2006 A Week 14 a, Prof. White 24

Static Random-Access Memory (SRAM) with CMOS Circuit in each cell EE 42/100, Spring 2006 Week 14 a, Prof. White 25

Power consumption in CMOS circuits EE 42/100, Spring 2006 Week 14 a, Prof. White 26

ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS – A REVIEW CASE 1 R t=0 Capacitor initially uncharged Charging i (Q=CVDD at end) V C DD RD Switch moves @ t=0 Power out of "battery" Power into C Power into R Energy out of "battery" Energy into C Energy into R (heat) ¥ EC = ò i. VC dt 0 1 = CVDD 2 2 EE 42/100, Spring 2006 Week 14 a, Prof. White This must be difference of E and EC, i. e. 1 CVDD 2 2 27

ENERGY AND POWER IN CHARGING R VDD t=0 C Energy out of "battery" Energy into C 1 = CVDD 2 2 RD Capacitor initially uncharged (Q=CVDD at end) Switch moves @ t=0 Energy into R (heat) 1 CVDD 2 2 In charging a capacitor from a fixed voltage source V DD half the energy from the source is delivered to the capacitor, and half is lost to the charging resistance, independent of the value of R. EE 42/100, Spring 2006 Week 14 a, Prof. White 28

ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS CASE 2 R t=0 Capacitor initially charged discharging (Q=CVDD) and discharges. V C DD RD i Switch moves @ t=0 Power out of C Power into RD Energy out of battery Energy out of C Energy into RD (heat) =0 ¥ EC = ò i. VC dt 0 Power out of battery =0 Power in/out of R =0 EE 42/100, Spring 2006 1 = CVDD 2 2 Week 14 a, Prof. White This must be energy initially in C, i. e. 1 CVDD 2 2 29

ENERGY IN DISCHARGING CAPACITORS R VDD t=0 C RD Capacitor initially charged (Q=CVDD) and discharges. Switch moves @ t=0 Energy out of C 1 = CVDD 2 2 Energy into RD (heat) 1 CVDD 2 2 When a capacitor is discharged into a resistor the energy originally stored in the capacitor (1/2 CVDD 2) is dissipated as heat in the resistor EE 42/100, Spring 2006 Week 14 a, Prof. White 30

• CMOS Power Consumption The total power consumed by a CMOS circuit is comprised of several components: 1. Dynamic power consumption due to charging and discharging capacitances*: f 0 1 = frequency of 0 1 transitions (“switching activity”) f = clock rate (maximum possible event rate) Effective capacitance CEFF = average capacitance charged every clock cycle * This is typically by far the dominant component! Other components of power dissipation are direct current flow during part of the CMOS switching cycle and leakage in the transistor junctions. EE 42/100, Spring 2006 Week 14 a, Prof. White 31

POWER DISSIPATION in DIGITAL CIRCUITS Each node transition (i. e. charging or discharging) results in a loss of (1/2)(C)(VDD 2) How many transitions occur per second? Well if the node is pulsed up then down at a frequency f (like a clock frequency) then we have 2 f dissipation events. A system of N nodes being pulsed at a frequency f to a signal voltage VDD will dissipate energy equal to (N) (2 f )(½CVDD 2) each second Therefore the average power dissipation is (N) (f )(CVDD 2) EE 42/100, Spring 2006 Week 14 a, Prof. White 32

LOGIC POWER DISSIPATION EXAMPLE Power = (Number of gates) x (Energy per cycle) x (frequency) P = (N) (CVDD 2) (f ) N = 107; VDD = 2 V; node capacitance = 10 f. F; f = 109 s-1 (1 GHz) P = 400 W! -- a toaster! Pretty high but realistic What to do? (N increases, f increases, hmm) 1) Lower VDD 2) Turn off the clock to the inactive nodes Clever architecture and design! Let’s define a as the fraction of nodes that are clocked (active). Then we have a new formula for power. EE 42/100, Spring 2006 Week 14 a, Prof. White 33

LOGIC POWER DISSIPATION with power mitigation Power = (Energy per transition) x (Number of gates) x (frequency) x fraction of gates that are active (a). P = a N CVDD 2 f In the last 5 years VDD has been lowered from 5 V to about 1. 5 V. It cannot go very much lower. But with clever design, we can make a as low as 1 or 10%. That is we do not clock those parts of the chip where there is no computation being made at the moment. Thus the 400 W example becomes 4 to 40 W, a manageable range (4 W with heat sink, 40 W with heat sink plus fan on the chip). EE 42/100, Spring 2006 Week 14 a, Prof. White 34

Low-Power Design Techniques 1. Reduce VDD → quadratic effect on Pdyn Example: Reducing VDD from 2. 5 V to 1. 25 V reduces power dissipation by factor of 4 – Lower bound is set by VT: VDD should be >2 VT 2. Reduce load capacitance → Use minimum-sized transistors whenever possible 3. Reduce the switching activity – involves design considerations at the architecture level (beyond the scope of this class!) EE 42/100, Spring 2006 Week 14 a, Prof. White 35