TD 5102 Embedded System in Silicon FPGA Architecture

TD 5102 Embedded System in Silicon FPGA Architecture and EDA Dr. Ha Yajun (E 1 -08 -17, elehy@nus. edu. sg) http: //courses. nus. edu. sg/course/elehy/TD 5102/ © NUS 2005 First. Name Last. Name – Activity / Group

Embedded Systems An embedded system is nearly any computing system (other than a general-purpose computer) with the following characteristics Single-functioned Typically, is designed to perform predefined function n Tightly constrained Tuned for low cost Single-to-fewer components based Performs functions fast enough Consumes minimum power n Reactive and real-time Must continually monitor the desired environment and react to changes n Hardware and software co-existence n © NUS 2005 Yajun Ha / ECE, NUS 2

Embedded Systems Examples: Communication devices Wired and wireless routers and switches n Automotive applications Braking systems, traction control, airbag release systems, and cruise-control applications n Aerospace applications Flight-control systems, engine controllers, auto-pilots and passenger in-flight entertainment systems n Defense systems Radar systems, fighter aircraft flight-control systems, radio systems, and missile guidance systems n © NUS 2005 Yajun Ha / ECE, NUS 3

Simplified and General Embedded System Design Methodology Algorithm Functional Modeling Algorithms Problem Partitioning Software Func. Model Software Development Architectural synthesis Application Source Code Structural RTL HDL Processors Application Specific Hardware(ASIC/FPGA) Platforms © NUS 2005 Yajun Ha / ECE, NUS Hardware Func. Model SW/HW Interface 4

Three Kinds of Embedded System Implementation Platform Choices Processor Reconfigurable FPGA + Rf +|-|*|>| D$ - > * Hardwired ASIC + - * > ID Sw I$ Sw + * > Programmable Sequential Instruction flow (cycle) Transfer bottleneck Power: © NUS 2005 100 Yajun Ha / ECE, NUS Configuration Configurable No wiring Parallel wired algorithm No configuration “Program” flow (occasionally) Overhead Distributed data 10 1 5

Why Use Reconfigurable Hardware? Processor- Processor. ASIC FPGA Performance Low High Flexibility High Low Power High Low Medium High Medium Why FPGAs ? • • © NUS 2005 Combine flexibility with performance. Shorter time-to-market and longer time-in-market. #FPGA gates/USD: 2004 1 M/10$. FPGA capacity: now 2004 50 Mgates => FPGAs get used as functional part of a design (<-> prototyping) Yajun Ha / ECE, NUS 6

Integration in System Design Integration of Functions Embedded Software Tools CPU Embedded Software Tools FPGA I/O Embedded Software Tools FPGA + Memory + IP + High Speed IO (4 K & Virtex ) Logic Design Tools Memor y Logic + Memory + IP + Processors + Rocket. IO (Virtex-II Pro ) Logic Design Tools Programmable Systems usher in a new era of system design integration possibilities Logic Design Tools Time © NUS 2005 Yajun Ha / ECE, NUS 7

FPGA Based Reconfigurable Platform E Reconfigurable Platforms Architectures n n n © NUS 2005 EDA for Reconfigurable Architectures Applications of Reconfigurable Platforms Lab Sessions on FPGA Board Yajun Ha / ECE, NUS 8

Simplified FPGA Architecture Functional Block I/O Block © NUS 2005 Yajun Ha / ECE, NUS All the three components can be re-programmed with configurations to implement application-specific digital circuits. Routing Network For example, each functional block can be programmed to implement a small amount of digital logic of a design; the routing network can be programmed to implement the design specific interconnection pattern; I/O blocks can be programmed to implement the input and output ports according to design requirements. 9

FPGA Reconfiguration Time 1 Time 2 Bitstream File 1 Bitstream File 2 All the programming information for the three programmable RA components is stored in a configuration file. The configuration file for a RA is often called a bitstream compared to a binary executable for a processor. Once a bitstream for a digital logic design is downloaded to a RA, the RA is programmed to implement the design. By providing different bitstreams, a single RA can be reprogrammed to implement different designs at different times. © NUS 2005 Yajun Ha / ECE, NUS 10

FPGA Functional Block Local Interconnect LE LE Functional Block Outputs …. . Functional Block Inputs LE Functional Block Internals Our target RAs use the Look-Up Table (LUT) type of functional block. Such a functional block is normally made of one or several logic elements (LE). They differentiate from each other mainly in terms of the input size of a LE and the number of LEs in a functional block. State-ofthe-art RAs normally use 4 -input LEs. © NUS 2005 Yajun Ha / ECE, NUS 11

FPGA Logic Element LE Internals The LE consists of a 16 SRAM cell Look-Up Table (LUT), and a flip flop (FF). The 16 SRAM cells LUT stores the truth table of any 4 -input logic function, thus it can implement any 4 -input logic function. The FF implements the storage element in a sequential circuit. © NUS 2005 Yajun Ha / ECE, NUS 12

LUT Content © NUS 2005 A B C D F 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 1 1 Yajun Ha / ECE, NUS A B C D F F = A*B+C*D The 16 SRAM cell LUT stores the output column of the truth table of the F function. The 4 inputs A, B, C and D will determine which bit the F value is for the current values of A, B, C and D. 13

Additional Computational Resources Memory blocks • Besides the LEs present in previous slide, some functional blocks in different target RAs have architecture specific features to improve the performance when implementing arithmetic functions. • These architecture specific features include carry logic, embedded memory blocks, multiplier and other hard cores. Microprocessor blocks © NUS 2005 Yajun Ha / ECE, NUS • Hard cores generally implement functions efficiently compared to FPGA functional blocks. 14

FPGA Routing Architecture A logic block input or output pin can connect to some or all of the wiring segments in the channel adjacent to it via a connection block of programmable switches. At every intersection of a horizontal channel and a vertical channel, there is a switch block. It is a set of programmable switches that allow some of the wire segments incident to the switch block to be connected to others. By turning on the appropriate switches, short wire segments can be connected together to form longer connections. © NUS 2005 Yajun Ha / ECE, NUS 15

FPGA Routing Wires • Some target RAs contain routing architectures that include different lengths of wires. • The length of a wire is the number of functional blocks it spans. • Left figures show wires of length 1, 2 and 4. © NUS 2005 Yajun Ha / ECE, NUS 16

XC 4000 Routing Architecture Example © NUS 2005 Yajun Ha / ECE, NUS 17

Commercial FPGA Architecture Comparison © NUS 2005 Yajun Ha / ECE, NUS 18

Power. PC-based Embedded Design Rocket. IO Dedicated Hard IP DSOCM BRAM Power. PC 405 Core PLB Processor Local Bus Hi-Speed Peripheral Off-Chip Memory © NUS 2005 Data e. g. Memory Controller ZBT SRAM Yajun Ha / ECE, NUS GB E-Net DDR SDRAM Bus Bridge Flexible Soft IP IBM Core. Connect™ DCR Bus on-chip bus standard OPB PLB, OPB, and DCR On-Chip Peripheral Bus Arbiter Instruction ISOCM BRAM UART SDRAM GPIO On-Chip Peripheral Full system customization to meet performance, functionality, and cost goals 19

Micro. Blaze-based Embedded Design Local Memory Micro. Blaze Bus 32 -Bit RISC Core Local. Link™ FIFO Channels 0, 1……. 32 Custom Functions Arbiter BRAM Configurable Sizes D-Cache Possible in BRAM Virtex-II Pro On-Chip Peripheral Bus Custom Functions Off-Chip Memory Yajun Ha / ECE, NUS Flexible Soft IP OPB UART © NUS 2005 I-Cache BRAM 10/100 E-Net On-Chip Peripheral FLASH/SRAM 20

FPGA Based Reconfigurable Platform § Reconfigurable Platforms Architectures EEDA for Reconfigurable Architectures n n © NUS 2005 Applications of Reconfigurable Platforms Lab Sessions on FPGA Board Yajun Ha / ECE, NUS 21

FPGA Design Flow © NUS 2005 Yajun Ha / ECE, NUS 22

Time Profile for Design Flow Steps Logic Optimization and routing steps normally consume the major part of the design flow time. © NUS 2005 Yajun Ha / ECE, NUS 23

FPGA Technology Mapping Technology step restructures the primitive logic gates, generated from the logic optimization step, into sets of 4 -input functional blocks. © NUS 2005 Yajun Ha / ECE, NUS 24

FPGA Placement and Routing The placement step finds physical locations for functional blocks, while the routing step finds physical routes for logic connections. © NUS 2005 Yajun Ha / ECE, NUS 25

Embedded Design in an FPGA Embedded design in an FPGA consists of the following: n FPGA hardware design n C drivers for hardware n Software design RTOS versus Main + ISR © NUS 2005

Embedded Development Tool Flow Overview Standard Embedded SW Development Flow Standard FPGA HW Development Flow C Code VHDL/Verilog Compiler/Linker Synthesizer (Simulator) Simulator Object Code Place & Route ? ? CPU code in off-chip memory CPU code in on-chip memory Download to FPGA Download to Board & FPGA Debugger © NUS 2005 Yajun Ha / ECE, NUS 27

Embedded Development Kit The Embedded Development Kit (EDK) consists of the following: n n n n Xilinx Platform Studio – XPS Base System Builder – BSB Create and Import Peripheral Wizard Hardware generation tool – Plat. Gen Library generation tool – Lib. Gen Simulation generation tool – Sim. Gen GNU software development tools System verification tool – XMD Virtual Platform generation tool - VPgen Software Development Kit (Eclipse) Processor IP Drivers for IP Documentation Use the GUI or the shell command tool to run EDK © NUS 2005 Detailed data sheet of Xilinx FPGA devices and user manuals of ISE and EDK tools are available online at http: //www. xilinx. com/support/library. htm

FPGA Based Reconfigurable Platform § Reconfigurable Platforms Architectures § EDA for Reconfigurable Architectures EApplications of Reconfigurable Platforms n © NUS 2005 Lab Sessions on FPGA Board Yajun Ha / ECE, NUS 29

Why Networked Hardware? --- Quoted from Cindy’s Boy Friend!!! Cindy Crawford asked me to encrypt our mobile phone talk!!! It is not an easy job!!! So I resort to hardware. But one day Cindy cried and told me that our talk had been disclosed. I laughed and said “Baby, never mind, I will change the encryption instantly through the network!!!” © NUS 2005 Yajun Ha / ECE, NUS 30

Future Networked Applications Need Client Platforms with Flexible Hardware Acceleration n Future networked applications can require high computing power up to 1000 Giga Ops [Nakatsuka, ISSCC’ 99], thus hardware acceleration is generally needed, and networked applications will contain both software and hardware components. n Different networked applications may use different industry standards to support new services, and require the client platforms to be flexible. n Networked applications usually work with a serverclient model, and require the client platforms to be connected to the network. © NUS 2005 Yajun Ha / ECE, NUS 31

Target Client Platform: Networked Reconfigurable Platform Application Description HW Part SW Part ISP 1 ISP 2 Dowloading ISPN static interconnect network ASIC Distr. memory arch. Reconfigurable Hardware Both ISP and reconfigurable HW can be programmed to flexible! adapt changing standards. n Reconfigurable HW can provide a better than ISP energy efficiency of high processing power vs. power consumption. High computing power! n Configurations for both ISP and reconfigurable HW can networked! be network downloaded. n © NUS 2005 Yajun Ha / ECE, NUS 32

Commercial FPGA Platform Up to 16 serial transceivers HW Part SW Part ISP 1 ISP 2 Dowloading Power. PCs Application Description ISPN static interconnect network ASIC Distr. memory arch. Reconfigurable Hardware Re. Config. logic Both ISP and reconfigurable HW can be programmed to flexible! adapt changing standards. n Reconfigurable HW can provide a better than ISP energyofefficiency Courtesy Xilinx (Virtexof. II high Pro) processing power vs. power consumption. High computing power! n Configurations for both ISP and reconfigurable HW can networked! be network downloaded. n © NUS 2005 Yajun Ha / ECE, NUS 33

Networked SW/HW Reconfiguration of Networked Information Appliance Advertise App on Web Page User Selects App User Downloads App Web Page Description ISP 1 Dowloading HW File © NUS 2005 Yajun Ha / ECE, NUS Java File ISP 2 ISPN static interconnect network ASIC Distr. memory arch. Re-configurable Hardware 34

Web MPEG Video Player Java MPEG Player + IDCT bitstream Server Side © NUS 2005 Yajun Ha / ECE, NUS CPU + FPGA Client Web Page Client Side 35

Networked Reconfiguration is Better Service Provider Service Request Service Client network Service II Data Streams © NUS 2005 Yajun Ha / ECE, NUS Service II Service I Reconfig …. . . Data Info Streams Service I Reconfig Info 36

FPGA Based Reconfigurable Platform § Reconfigurable Platforms Architectures § EDA for Reconfigurable Architectures § Applications of Reconfigurable Platforms ELab Sessions on FPGA Board E Lab Session 1: Reconfigurable fabric based hardware design E Lab Session 2: Processor+Reconfig Fabric based system design © NUS 2005 Yajun Ha / ECE, NUS 37

MEMEC Virtex-4 LC FPGA Board Serial Port FPGA Push Buttons DIP Switches LEDs More FPGA board related documentations have been put online at http: //courses. nus. edu. sg/course/elehy/EE 4218/projects. htm © NUS 2005 Yajun Ha / ECE, NUS 38

FPGA Board Demo 7 -segment Display When PUSH 2 (SW 5) is not held down, the 7 -segment display (DD 1) does a binary-to-hex conversion of the binary number represented by the 4 -bit DIP switch (SW 3). n When PUSH 2 (SW 5) is held down, the 7 -segment display (DD 1) counts from 0 -9. n SW 5 PUSH 2 LED 1, LED 2, LED 3, and LED 4 count in binary from 0 -9 (matching what is on DD 1 when PUSH 2 is pressed). n Pushing PUSH 1 resets the counter. n © NUS 2005 Yajun Ha / ECE, NUS 39

FPGA Lab 1 & 2 n Please print relevant docs by yourself and bring to labs! n Watch the FPGA board demo closely n Lab 1: Try to re-implement the demo with Xilinx ISE on your FPGA board and do the assignment n Design files for the demo will be installed on your PC. n You need to use Xilinx ISE tool to generate and download the bitstream. n Get familiar with Xilinx ISE environment and link the various FPGA design flow steps to the tool. n Browse and understand the design files for the demo. n Lab 2: Follow the Xilinx EDK tutorial that can be found in the TD 5102 course web site under project page. Lab session in Signal Processing and VLSI Lab (E 4 -08 -34) 2: 00 -5: 00 pm on 13 & 14 Dec! © NUS 2005 Yajun Ha / ECE, NUS 40

Summary n FPGA n EDA architectures have been introduced. tools for FPGAs have been introduced. n Applications of FPGA for networked platforms have been introduced. n Lab © NUS 2005 Yajun Ha / ECE, NUS introduction. 41