Synchronous logic Library IEEE use IEEE stdlogic1164 all

Synchronous logic Library IEEE; use IEEE. std_logic_1164. all; entity dff is port ( d, clk: in std_logic; q : out std_logic); end dff;

Architecture dff_a of dff is begin process(clk) begin if (clk‘event and clk = ‘ 1’ ) then q <= d; end if; end process; end dff_a ;

Level sensitive latch process(clk, d) begin if ( clk = ‘ 1’ ) then q <= d; end if; end process;

T flip-flop Library IEEE; use IEEE. std_logic_1164. all; entity tff is port ( t , clk: in std_logic; q : buffer std_logic); end tff;

Architecture tff_a of tff is begin process(clk) begin if (clk‘event and clk = ‘ 1’ ) then if ( t = ‘ 1’ ) then q <= not (q) ; else q <= q; end if; end process; end tff_a ;

An 8 bit register Library IEEE; use IEEE. std_logic_1164. all; entity reg 8 is port ( d: in std_logic_vector(7 downto 0); clk: in std_logic; q : out std_logic_vector(7 downto 0)); end reg 8;

Architecture reg_a of reg 8 is begin process(clk) begin if (clk ‘ event and clk = ‘ 1’ ) then q <= d; end if; end process; end reg_a ;

Wait Until Statement • It can be used to describe the behavior of registered circuits. • A process that has a wait statement cannot have a sensitivity list. • The wait until statement must be the first in a process. • Synchronous logic described with a wait statement cannot be asynchronously reset.

Architecture dff_a of dff is begin process begin wait until(clk‘event and clk = ‘ 1’ ) then q <= d; end process; end dff_a ;

Rising_edge and Falling_edge • The std_logic_1164 package defines the functions ‘rising_edge’ and ‘falling_edge’. • These functions can be used in place of clk’event and clk = ‘ 1’.

Asynchronous reset Architecture async_reset_a of dff is begin process(clk, reset) begin if (reset = ‘ 1’) then q <= ‘ 0’; elsif (clk‘event and clk = ‘ 1’ ) then q <= d; end if; end process; end async_reset_a ;

Asynchronous preset Architecture async_preset_a of dff is begin process(clk, preset) begin if (preset = ‘ 1’) then q <= ‘ 1’; elsif (clk‘event and clk = ‘ 1’ ) then q <= d; end if; end process; end async_preset_a ;

Synchronous resets and presets Architecture sync_reset_a of dff is begin process(clk, reset) begin if (clk‘event and clk = ‘ 1’ ) then if (reset = ‘ 1’) then q <= ‘ 0’; else q <= d; end if; end process;

• Architecture count 4_a of count is • signal count_int : std_logic_vector( 3 downto 0); • begin • process( reset , clk) • begin • if ( reset = ‘ 0’); • then count_int <= ( others => ‘ 0’);

Bin_count 3 • Architecture beh of bin_count 3 is • signal q_int : std_logic_vector( 2 downto 0 ); • begin • process( clk) • begin • if( clk = ‘ 1’ and clk’event) then

• if( reset = ‘ 1’) then • q_int <= “ 000”; • elsif( load = ‘ 1’) then • q_int <= data_in ; • else • q_int <= q_int + 1; • end if; • end process; • q <= q_int; • end beh;

• • elsif( clk = ‘ 1’ and clk’event) then if( count_enable = ‘ 1’ then count_int <= count_int + 1; end if; end process; q <= count_int; end count 4_a;

Library IEEE; use IEEE. std_logic_1164. all; entity reg 8 is port ( d: in std_logic_vector(7 downto 0); clk , reset, set: in std_logic; q : out std_logic_vector(7 downto 0)); end reg 8;

Architecture reg_a of reg 8 is begin process(clk, reset) begin if (reset = ‘ 1’ ) then q <= (others => ‘ 0’); elsif (clk‘event and clk = ‘ 1’ ) then if (set = ‘ 1’) then q <= (others => ‘ 1’); else q <= d; end if; end process; end reg_a ;

Library ieee; use ieee. Std_logic_1164. all; use work. numeric_std. all; Entity counter 8 is Port(data: in unsigned (7 downto 0); txclk, grst : in std_logic; q: out std_logic_vector(7 downto 0) ); end counter 8;

architecture counter 8_a counter 8 is signal count : std_logic_vector(7 downto 0); begin count: process (txclk, grst) begin. If (grst = ‘ 1’) then count <= “ 00111010”;

elsif( txclk’event and txclk = ‘ 1’) then if ( load = ‘ 1’) then count <= data; elsif ( enable = ‘ 1’) then count <= count + 1; end if; end process; q <= count; end counter_8_a;

Library ieee; Use ieee. Std_logic_1164. All; Use work. Numeric_std. all; Entity cnt 8 is Port (txclk, grst, gpst : in std_logic ; enable, load : in std_ logic; data : in unsigned (7 down to 0); q : buffer unsigned (7 down to 0)); end cnt 8;

architecture cnt 8_a of cnt 8 is begin count : process (grst, gpst, txclk) begin if (grst=‘ 1’) then _asynchronously reset ‘q’ to 0 s’. q <= (others => ‘ 0’); elsif (gpst = ‘ 1’ 0 then -- asynchronously set ‘q’ to all 1 s’.

q <= (others => ‘ 1’); elsif (txclk’ event and txclk = ‘I’) then if (load = ‘ 1’) then q <= data; elsif (enable = ‘ 1’) then q <= q + 1; end if; end process; end cnt 8_a;

The wait until statement can also be used to describe synchronous logic with preset and resets, but these resets and presets must be synchronous. This is because the wait statement must be the first statement in the process and any statements that come after it describe synchronous logic.

Library ieee; Use ieee. Std_logic_1164. all; Use work. Std_arith. all; Entity cnt 8 is Port ( txclk, grst : in std_logic; enable, load : in std_logic; 0 e : in std_logic; data : in std_logic_vector (7 downto 0); Cnt_out : out std_logic_vector (7 down to 0)); end cnt 8;

architecture cnt 8_a of cnt 8 is signal cnt : std_logic_vector (7 down to 0); begin Count : process (grst, txclk) begin if (grst= ‘ 1’) then cnt <= (others => ‘ 0’); elsif (txclk’ event and txclk = ‘ 1’) then if (load = ‘ 1’) then. Cnt <= data; elsif (enable = ‘ 1’) then Cnt <= cnt +1; end if; end process count;

Oes : process (oe, cnt) Begin If (oe=‘ 1) then Cnt_out <= cnt; else cnt_out <= (others => ‘Z’); end if end process oes; ed cnt 8_a;

Library ieee; Use ieee. Std_logic_1164. all; Use work. Std_arith. all; Entity cnt 8 is Port ( txclk, grst : in std_logic; enable, load : in std_logic; Oe : in std_logic; Cnt_out : inout std_logic_vector (7 down to 0)); end cnt 8; architecture cnt 8_a of cnt 8 is

begin count : process (grst, txclk) begin if (grst = ‘ 1’) then cnt <= (others => ‘ 0’); elsif (txclk’ event and txclk = ‘ 0’) then if (load = ‘ 1’ ) then. Cnt <= cnt_out; elsif (enable = ‘ 1’) then Cnt <= cnt + 1; end if; end process count;

Oes : process (oe, cnt) begin if (oe = ‘ 0’) then Cnt_out <= (others => ‘z’); else Cnt_out <= cnt; end if; end process oes; end cnt 8_a;

This circuit accepts 8 -bit input data, loads this data into a register and, went load input signal is low, rotates this data by one bit with each rising edge clock signal. The circuit is provided within asynchronous reset, and the data stored in the register is accessible via the output signal Q.

- - eight_bit barrel shifter library ieee; use ieee. std_logic_1164. all; entity rotate is port ( clk, rst, load : in std_ulogic ; data : in std_ulogic_vector (0 to 7 ) ; Q : out std_ulogic_vector (0 to 7 ) ); end rotate ;

architecture rotate 1 of rotate is begin reg : process (rst, clk) variable Qreg : std_ulogic_vector (0 to 7) ; begin if (Rst = ‘ 1’ then - - async reset Qreg : = “ 0000’ ;

elsif (clk = ‘ 1’ and ‘clk’event ) then if (load = ‘ 1’ ) then Qreg : = data; else Qreg : = Qreg (1 to 7 ) & Qreg (0) ; end if ; Q <= Qreg ; end process ; end rotate ;

Synchronous logic design Why use synchronous logic ? ·Synchronous designs eliminate problems associated with speed variations through different paths of logic. By sampling ·signals at well-defined time intervals, fast paths and slow paths can be handled simply.

·Synchronous designs work well under variations of temperature, ·voltage, and process. This stability is key for high-volume manufacturing. ·Many designs must be portable. ·They must be easily migratable to a new and improved technology (for example, moving from 0. 6 um to 0. 35 microns).

·The deterministic behavior of synchronous designs makes the process of moving to a new technology very straightforward. Interfacing between two blocks of logic is simplified by defining standardized synchronous behavior.

·Asynchronous interfaces demand elaborate handshaking (or token passing ) to ensure integrity of information. However, synchronous designs with known timing characteristics can guarantee correct reception of data.

·Synchronous circuits are made with a mixture of combinatorial logic and clocked elements, such as flip-flops or registers. The clocked elements share a common clock, and all transition from one state to another on the rising edge of the clock. When the rising edge occurs, the registers propagate logic levels at their D inputs to the Q outputs.

·Stetup time (Tsu) : Setup time is the time that a register’s ·D input must be valid before the clock transitions. ·Hold Time (Th) : Hold time is the period that a register’s · D input must be valid after the clock has transitioned.

Clock distribution ·Skew Minimization : Clock skew is the variation ·in time of the clock’s active transition begin detected by ·different devices within a system. · Skew must be kept to a minimum to ensure that setup ·and hold times are not violated at any

·Clock Fidelity : The clock’s wave-form must be as · clean and deterministic as possible. · Techniques used to guarantee consistent clock ·behavior include transmissionline termination, ·ground-bounce minimization, and the use of