CLOCK library ieee use ieee stdlogic1164 all entity

CLOCK 설계 library ieee; use ieee. std_logic_1164. all; entity clockdiv is port ( clk 25 mhz: in std_logic; clk: out std_logic); end clockdiv; architecture rtl of clockdiv is constant max: integer : = 10000000; constant half: integer : = max/2; signal count: integer range 0 to max; begin process begin wait until clk 25 mhz'event and clk 25 mhz = '1'; if count < max then count <= count + 1; else count <= 0; end if; if count < half then clk <= '0'; else clk <= '1'; end if; end process; end rtl;

DECODER 설계 library ieee; use ieee. std_logic_1164. all; entity decoder is port ( i: in std_logic_vector(3 downto 0); an, bn, cn, dn, en, fn, gn: out std_logic); end decoder; -- 4 -bit input to decoder -- the 7 -segment outputs "abcdefg" architecture rtl of decoder is signal segments: std_logic_vector(1 to 7); begin process(i) begin case i is when "0000" => segments <= "1111110"; when "0001" => segments <= "0110000"; when "0010" => segments <= "1101101"; when "0011" => segments <= "1111001"; when "0100" => segments <= "0110011"; when "0101" => segments <= "1011011"; when "0110" => segments <= "1011111"; when "0111" => segments <= "1110000"; when "1000" => segments <= "1111111"; when "1001" => segments <= "1110011"; when "1010" => segments <= "1110111"; when "1011" => segments <= "0011111"; when "1100" => segments <= "1001110"; when "1101" => segments <= "0111101"; when "1110" => segments <= "1001111"; when "1111" => segments <= "1000111"; when others => segments <= "0000000"; end case; end process; an <= not segments(1); bn <= not segments(2); cn <= not segments(3); dn <= not segments(4); en <= not segments(5); fn <= not segments(6); gn <= not segments(7); end rtl --------- 0 1 2 3 4 5 6 7 8 9 a b c d e f all off -- a 1 turns on the led

COUNTER 설계 library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_unsigned. all; entity counter is port ( clock: in std_logic; clear: in std_logic; count: in std_logic; q: out std_logic_vector(3 downto 0); overflow: out std_logic); end counter; -- output of the counter -- input clock source -- clear counter to 0 -- to count architecture rtl of counter is signal countvalue: std_logic_vector(3 downto 0); -- to remember the count as a 4 -bit value begin process(clock, clear, count) begin if (clear = '1' ) then countvalue <= "0000"; -- reset the count to 0 when resetn is low elsif (clock'event and clock = '1') then if (count = '1') then countvalue <= countvalue + "0001"; -- increment the count by 1 end if; end process; overflow <= '1' when countvalue = "1111" else '0'; q <= countvalue; assign the count to the counter output end rtl; --

UPFLEX 설계 LIBRARY IEEE; USE IEEE. STD_LOGIC_1164. ALL; COMPONENT Counter PORT ( Clock: IN STD_LOGIC; Clear: IN STD_LOGIC; Count: IN STD_LOGIC; Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); Overflow: OUT STD_LOGIC); END COMPONENT; ENTITY up 2 flex IS PORT ( Clock_25 MHz: IN STD_LOGIC; Reset. N: IN STD_LOGIC; Stop. N: IN STD_LOGIC; a. N, b. N, c. N, d. N, e. N, f. N, g. N, Overflow: OUT STD_LOGIC; Vcc: OUT STD_LOGIC_VECTOR(1 TO 8)); END up 2 flex; ARCHITECTURE structural OF up 2 flex IS -- declares the three components to use COMPONENT Clockdiv PORT ( Clk 25 Mhz: IN STD_LOGIC; Clk: OUT STD_LOGIC); END COMPONENT; COMPONENT Decoder PORT ( I: IN STD_LOGIC_VECTOR(3 DOWNTO 0); a. N, b. N, c. N, d. N, e. N, f. N, g. N: OUT STD_LOGIC); END COMPONENT; components BEGIN together END structural; -- internal signals for doing the connections between the SIGNAL Clock, Reset, Over: STD_LOGIC; SIGNAL Q: STD_LOGIC_VECTOR(3 DOWNTO 0); -- use structural level coding to connect the three components U 0: Clockdiv PORT MAP (Clock_25 MHz, Clock); U 1: Counter PORT MAP (Clock, Reset, Stop. N, Q, Over); U 2: Decoder PORT MAP (Q, a. N, b. N, c. N, d. N, e. N, f. N, g. N); Reset <= NOT Reset. N; Overflow <= NOT over; Vcc <= "1111";