Library ieee Use ieee stdlogic1164 all Entity gate

数字逻辑单元设计-基本逻辑门电路设计 基本门电路的设计 Library ieee; Use ieee. std_logic_1164. all; Entity gate is Port(a, b, c : in std_logic; d : out std_logic); end gate; architecture rtl of gate is begin d<=((not a) and b) or c; end rtl;

数字逻辑单元设计-编码器设计 　 8/3线编码器的VHDL描述 library ieee; use ieee. std_logic_1164. all; entity priority_encoder_1 is port ( sel : in std_logic_vector (7 downto 0); code : out std_logic_vector (2 downto 0)); end priority_encoder_1; architecture archi of priority_encoder_1 is begin code <= "000" when sel(0) = '1' else "001" when sel(1) = '1' else "010" when sel(2) = '1' else "011" when sel(3) = '1' else "100" when sel(4) = '1' else "101" when sel(5) = '1' else "110" when sel(6) = '1' else "111" when sel(7) = '1' else "ZZZ"; end archi;

数字逻辑单元设计-译码器设计 十六进制数的共阳极7段数码显示VHDL描述 library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_unsigned. all; entity decoder is port(hex: in std_logic_vector(3 downto 0); led : out std_logic_vector(6 downto 0)); end decoder; architecture rtl of decoder is begin with hex select LED<= "1111001" when "0001", --1 "0100100" when "0010", --2 "0110000" when "0011", --3 "0011001" when "0100", --4 "0010010" when "0101", --5 "0000010" when "0110", --6 "1111000" when "0111", --7 "0000000" when "1000", --8 "0010000" when "1001", --9 "0001000" when "1010", --A "0000011" when "1011", --b "1000110" when "1100", --C "0100001" when "1101", --d "0000110" when "1110", --E "0001110" when "1111", --F "1000000" when others; --0 end rtl;

数字逻辑单元设计-数据选择器设计设计 4选1多路选择器的IF语句描述 library ieee; use ieee. std_logic_1164. all; entity multiplexers_1 is port (a, b, c, d : in std_logic; s : in std_logic_vector (1 downto 0); o : out std_logic); end multiplexers_1; architecture archi of multiplexers_1 is begin process (a, b, c, d, s) begin if (s = "00") then o <= a; elsif (s = "01") then o <= b; elsif (s = "10") then o <= c; else o <= d; end if; end process; end archi;

数字逻辑单元设计-数据选择器设计设计 4选1多路选择器的CASE语句描述 library ieee; use ieee. std_logic_1164. all; entity multiplexers_2 is port (a, b, c, d : in std_logic; s : in std_logic_vector (1 downto 0); o : out std_logic); end multiplexers_2; architecture archi of multiplexers_2 is begin process (a, b, c, d, s) begin case s is when "00" => o <= a; when "01" => o <= b; when "10" => o <= c; when others => o <= d; end case; end process; end archi;

数字逻辑单元设计-数字比较器 8位数据比较器的VHDL描述 library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_unsigned. all; entity comparator_1 is port(A, B : in std_logic_vector(7 downto 0); CMP : out std_logic); end comparator_1; architecture archi of comparator_1 is begin CMP <= '1' when A >= B else '0'; end archi; 　从上面的例子可以看出，使用VHDL中的>、>=、<、<=、=、 /=，这几种关系运算符及其它们的组合，可以设计出具有复杂比 较功能的比较器。

数字逻辑单元设计-总线缓冲器 三态门的进程描述 Library ieee; Use ieee. std_logic_1164. all; Entity tri_gate is Port (en : in std_logic; din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(7 downto 0)); end tri_gate; Architecture rtl of tri_gate is begin process(din, en) begin if(en=’ 1’) then dout<=din; else dout<=’ZZZZ’; end if; end process; end rtl;

数字逻辑单元设计-总线缓冲器 三态门的WHEN-ELSE进程描述 Library ieee; Use ieee. std_logic_1164. all; Entity tri_gate is Port (en : in std_logic; din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(7 downto 0)); end tri_gate; Architecture rtl of tri_gate is begin dout<= din when en ='1' else 'ZZZZ'; end rtl; 从上面的两个例子中可以看出，使用条件并行语句描述三态 门比使用进程要简单的多。

数字逻辑单元设计-总线缓冲器 双向总线缓冲器的描述 Library ieee; Use ieee. std_logic_1164. all; Entity bidir is Port(a : inout std_logic_vector(15 downto 0)); End bidir; Architecture rtl of bidir is signal a_in : std_logic_vector(15 downto 0); signal a_out : std_logic_vector(15 downto 0); signal T : std_logic; Begin a<= a_out when T = '0' else "ZZZZZZZZ"; a_in<=a; end rtl;

数字逻辑单元设计-加法器设计 带进位输入和输出的无符号的8比特加法器的VHDL描述 library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_arith. all; use ieee. std_logic_unsigned. all; entity adders_4 is port(A, B, CI : in std_logic_vector(7 downto 0); 　　SUM : out std_logic_vector(7 downto 0); 　　CO : out std_logic); end adders_4; architecture archi of adders_4 is 　signal tmp: std_logic_vector(8 downto 0); begin 　SUM <= tmp(7 downto 0); 　CO <= tmp(8); 　tmp <= conv_std_logic_vector((conv_integer(A) + conv_integer(B) 　 　+conv_integer(CI)), 9); end archi;

数字逻辑单元设计-减法器设计 【例4 -10】无符号 8位带借位的减法器的VHDL描述 library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity adders_8 is port(A, B : in std_logic_vector(7 downto 0); BI : in std_logic; RES : out std_logic_vector(7 downto 0)); end adders_8; architecture archi of adders_8 is begin RES <= A - BI; end archi;

数字逻辑单元设计-ALU设计 考虑下面的几个例子(最高位为符号位)： 1）5310+2510=3516+1916=7810=4 E 16, cf=0, ovf=0 2）5310+9110=3516+5 B 16=14410=9016, cf=0, ovf=1 3）5310 -4510=3516+D 316=810=10816, cf=1, ovf=0 4）-9810 -4510=9 E 16+D 316=-14310=17116, cf=1, ovf=1 当满足条件：（第六位向第七位进位） xor （第七位向cf进位）时，ovf=1

数字逻辑单元设计-ALU设计 library IEEE; ---库声明及调用 use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity alu 4 is port( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); alusel : in std_logic_vector(2 downto 0); y : out std_logic_vector(3 downto 0); nf : out std_logic; zf : out std_logic; cf : out std_logic; ovf : out std_logic ); end alu 4;

数字逻辑单元设计-ALU设计 architecture Behavioral of alu 4 is --功能描述 begin process(a, b, alusel) variable temp : std_logic_vector(4 downto 0): ="00000"; variable y_temp : std_logic_vector(3 downto 0): ="0000"; begin cf<='0'; ovf<='0'; case alusel is when "000"=> y_temp: =a; when "001"=> temp: =('0'&a)+('0'&b); y_temp: =temp(3 downto 0); cf<=temp(4); ovf<=temp(3) xor a(3) xor b(3) xor temp(4);

数字逻辑单元设计-ALU设计 when "010"=> temp: =('0'&a)-('0'&b); y_temp: =temp(3 downto 0); cf<=temp(4); ovf<=temp(3) xor a(3) xor b(3) xor temp(4); when "011"=> temp: =('0'&b)-('0'&a); y_temp: =temp(3 downto 0); cf<=temp(4); ovf<=temp(3) xor a(3) xor b(3) xor temp(4);

数字逻辑单元设计-ALU设计 when "100"=> y_temp: =not a; when "101"=> y_temp: =a and b; when "110"=> y_temp: =a or b; when "111"=> y_temp: =a xor b; when others=> y_temp: =a; end case;

数字逻辑单元设计-ALU设计 nf<=y_temp(3); y<=y_temp; if(temp="0000") then zf<='1'; else zf<='0'; end if; end process; end Behavioral;

数字逻辑单元设计-乘法器设计 下面给出一个 8位和4位无符号的乘法器的VHDL描述 library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_unsigned. all; entity multipliers_1 is port(A : in std_logic_vector(7 downto 0); B : in std_logic_vector(3 downto 0); RES : out std_logic_vector(11 downto 0)); end multipliers_1; architecture beh of multipliers_1 is begin RES <= A * B; end beh;

数字逻辑单元设计-除法器设计 除法器的VHDL描述。 library ieee; use ieee. std_logic_1164. all; use entity divider_1 is port(DI : in unsigned(7 downto 0); DO : out unsigned(7 downto 0)); end divider_1; architecture archi of divider_1 is begin DO <= DI / 2; end archi;

数字逻辑单元设计-除法器设计(任意除数) 除数不为 2的整数幂的除法器VHDL描述 library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity div 8 is port( numerator : in std_logic_vector(7 downto 0); denominator : in std_logic_vector(3 downto 0); quotient : out std_logic_vector(7 downto 0); remainder : out std_logic_vector(3 downto 0) ); end div 8;

数字逻辑单元设计-除法器设计(任意除数) architecture Behavioral of div 8 is begin process(numerator, denominator) variable n 1 : std_logic_vector(4 downto 0); variable n 2 : std_logic_vector(7 downto 0); variable numer : std_logic_vector(7 downto 0); variable d : std_logic_vector(4 downto 0); Begin n 1: ="00000"; n 2: ="0000"; numer: =numerator; d: ='0' & denominator; quotient<=n 2(7 downto 0); remainder<=n 1(3 downto 0);

数字逻辑单元设计-除法器设计(任意除数) for i in 0 to 7 loop for j in 4 downto 1 loop n 1(j): =n 1(j-1); end loop; n 1(0): =numer(7); for k in 7 downto 1 loop numer(k): =numer(k-1); end loop; numer(0): ='0'; for l in 7 downto 1 loop n 2(l): =n 2(l-1); end loop; if(n 1(4 downto 0)>=d) then n 1: =n 1 -d; n 2(0): ='1'; else n 1: =n 1; n 2(0): ='0'; end if; end loop; end process;

数字逻辑单元设计-D触发器设计 Library ieee; Useieee. std_logic_1164. all; Entity fdd is Port(clk, d, clr, pre, ce : in std_logic; q : out std_logic); end fdd; architecture rtl of dff is signal q_tmp : std_logic; begin q<=q_tmp; process(clk, clr, pre, c) begin if(clr=’ 1’) then q_tmp<=’ 0’; elsif(pre=’ 1’) then q_tmp<=’ 1’; elsif rising_edge(clk) then if(ce=’ 1’) then q_tmp<=d; else q_tmp<=q_tmp; end if; end process; end rtl;

数字逻辑单元设计-JK触发器设计 带时钟使能和异步复位/置位的JK 触发器的VHDL描述 Library ieee; Use ieee. std_logic_1164. all; Entity fdd is Port(s, r, j, k, ce, c: in std_logic; q : out std_logic); end fdd; architecture rtl of dff is signal q_tmp : std_logic; begin q<=q_tmp; process(s, r, c) begin if(r=’ 1’) then q_tmp<=’ 0’; elsif(s=’ 1’) then q_tmp<=’ 1’; elsif rising_edge(clk) then if(ce=’ 0’) then q_tmp<=q_tmp; else if(j=’ 0’ and k=’ 1’) then q_tmp<=’ 0’; elsif(j=’ 1’ and k=’ 0’) then q_tmp<=’ 1’; elsif(j=’ 1’ and k=’ 1’) then q_tmp<=not q_tmp; end if; end process; end rtl;

数字逻辑单元设计-RS触发器设计 library ieee; use ieee. std_logic_1164. all; entity rsff is port(r, s, clk : in std_logic; q, qn : out std_logic); end rsff; architecture rtl of rsff is signal q_tmp : std_logic; begin q<=q_tmp; process(clk) begin if rising_edge(clk)then if (s = ‘ 1’ and r = ‘ 0’) then q_tmp<=‘ 1’; elsif (s=‘ 0’ and r=‘ 1’) then q_tmp<=’ 0’; elsif (s=‘ 0’ and r=‘ 0’) then q_tmp<=q_tmp; else null; end if; end process; end rtl;

数字逻辑单元设计-锁存器设计 Library ieee; Use ieee. std_logic_1164. all; Entity latch is Port(gate, data, set : in std_logic; Q : out std_logic); End latch; Architecture rtl of latch is Begin process(gate, data, set) Begin if(set=’ 0’) then Q<=’ 1’; elsif(gate=’ 1’) then Q<=data; end if; end process; end rtl;

数字逻辑单元设计-通用计数器设计 architecture Behavioral of count 3 bit is begin 3位计数器的VHDL语言行为级描述 process(clr, clk) begin library IEEE; use IEEE. STD_LOGIC_1164. ALL; if(clr='1') then use IEEE. STD_LOGIC_ARITH. ALL; q<="000"; use IEEE. STD_LOGIC_UNSIGNED. ALL; elsif(rising_edge(clk)) then entity count 3 bit is q<=q+1; Port ( clr : in STD_LOGIC; end if; clk : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (2 downto 0)); end process; end count 3 bit; end Behavioral;

数字逻辑单元设计-带模计数器设计 architecture Behavioral of mod 5 cnt is 5进制计数器的VHDL语言行为级描述 begin process(clk, clr) begin library IEEE; if(clr='1') then use IEEE. STD_LOGIC_1164. ALL; q<="000"; use IEEE. STD_LOGIC_ARITH. ALL; elsif(rising_edge(clk)) then use IEEE. STD_LOGIC_UNSIGNED. ALL; if(q="100") then entity mod 5 cnt is q<="000"; Port ( clr : in STD_LOGIC; else clk : in STD_LOGIC; q<=q + 1; q : inout STD_LOGIC_VECTOR (2 downto 0)); end if; end mod 5 cnt; end if; end process; end Behavioral;

数字逻辑单元设计-时钟分频器设计 时钟分频器VHDL语言行为级描述 library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity clkdiv is Port ( clk : in STD_LOGIC; clr : in STD_LOGIC; clk 190 : out STD_LOGIC; clk 48 : out STD_LOGIC); end clkdiv; architecture Behavioral of clkdiv is signal q : std_logic_vector(24 downto 0); begin process(clr, clk) begin if(clr='1') then q<=(others=>'0'); elsif(rising_edge(clk)) then q <= q + 1; end if; end process; clk 190 <= q(17); --190 Hz clk 48 <= q(19); --47. 7 Hz end Behavioral;

数字逻辑单元设计-移位寄存器设计 1、预定义的移位操作符 （1）算术左移的VHDL描述 <signed_sig>/<unsigned_sig> sla <shift_amount_in_integer> （2）逻辑左移的VHDL描述 <signed_sig>/<unsigned_sig> sll <shift_amount_in_integer> （3）算术右移的VHDL描述 <signed_sig>/<unsigned_sig> sra <shift_amount_in_integer> （4）逻辑右移的VHDL描述 <signed_sig>/<unsigned_sig> srl <shift_amount_in_integer>

数字逻辑单元设计-移位寄存器设计 【例4 -26】移位操作符实现逻辑左 移的VHDL描述 library ieee; use ieee. std_logic_1164. all; use ieee. numeric_std. all; entity logical_shifters_2 is port(DI : in unsigned(7 downto 0); SEL : in unsigned(1 downto 0); SO : out unsigned(7 downto 0)); end logical_shifters_2; architecture archi of logical_shifters_2 is begin process(<clock>) begin if ( <clock>'event and <clock> ='1') then case SEL is when "00" => SO<= DI ; when "01" => SO <= DI sll 1; when "10" => SO<= DI sll 2; when "11" => SO <=DI sll 3; when others => SO<= DI ; end case; end if; end process; end archi;

数字逻辑单元设计-移位寄存器设计 【例4 -27】元件例化的方法实现 16位 串入/串出移位寄存器的VHDL描述 Library ieee; Use ieee. std_logic_1164. all; Entity shift 8 is Port (a, clk : in std_logic; B : out std_logic); End shift 8; Architecture rtl of shift 8 is Component dff Port(d, clk : in std_logic; Q : out std_logic); End component; Signal z : std_logic_vector(15 downto 0); Begin z(0)<=a; G 1: for i in 0 to 15 generate Dffx : dff port map(z(i), clk, z(i+1)); End generate; b<=z(15); end rtl;

数字逻辑单元设计-移位寄存器设计 【例4 -28】类型操作实现 16位 移位寄存器的VHDL描述 library ieee; use ieee. std_logic_1164. all; entity shift_registers_1 is port(C, SI : in std_logic; SO : out std_logic); end shift_registers_1; architecture archi of shift_registers_1 is signal tmp: std_logic_vector(15 downto 0); begin SO <= tmp(7); process (c) begin if rising_edge(c) then for i in 0 to 14 loop tmp(i+1) <= tmp(i); end loop; tmp(0) <= SI; end if; end process; end archi;

数字逻辑单元设计-移位寄存器设计 【例4 -29】并置操作实现 16位串入/ 并出移位寄存器的VHDL描述 library ieee; use ieee. std_logic_1164. all; entity shift_registers_5 is port(C, SI : in std_logic; PO : out std_logic_vector(15 downto 0)); end shift_registers_5; architecture archi of shift_registers_5 is signal tmp: std_logic_vector(7 downto 0); begin PO <= tmp; process (C) begin if rising_edge(C) then tmp <= tmp(14 downto 0)& SI; end if; end process; end archi;

数字逻辑单元设计-环形移位寄存器设计 4位右移环形移位寄存器的VHDL语言描述 library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity ring_shiftreg 4 is Port ( clk : in STD_LOGIC; clr : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0)); end ring_shiftreg 4; architecture Behavioral of ring_shiftreg 4 is begin process(clr, clk) begin if(clr='1') then q<="0001"; elsif(rising_edge(clk)) then q(3) <= q(0); q(2 downto 0) <= q(3 downto 1); end if; end process; end Behavioral;

数字逻辑单元设计-消抖电路设计 消抖电路的VHDL语言描述 library IEEE; process(cclk, clr, inp) use IEEE. STD_LOGIC_1164. ALL; begin use IEEE. STD_LOGIC_ARITH. ALL; if(clr='1') then use IEEE. STD_LOGIC_UNSIGNED. ALL; delay 1<="0000"; entity debounce 4 is delay 2<="0000"; Port ( delay 3<="0000"; inp : in STD_LOGIC_VECTOR (3 downto 0); elsif(rising_edge(cclk)) then cclk : in STD_LOGIC; delay 1<=inp; clr : in STD_LOGIC; delay 2<=delay 1; outp : out STD_LOGIC_VECTOR (3 downto 0)); delay 3<=delay 2; end debounce 4; end if; end process; architecture Behavioral of debounce 4 is outp<=delay 1 and delay 2 and delay 3 signal delay 1, delay 2, delay 3 : std_logic_vector(3 end Behavioral; downto 0); begin

数字逻辑单元设计-时钟脉冲电路设计 时钟脉冲生成的VHDL语言描述 library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity clock_pluse is Port ( inp : in STD_LOGIC; cclk : in STD_LOGIC; clr : in STD_LOGIC; outp : out STD_LOGIC); end clock_pluse; architecture Behavioral of clock_pluse is signal delay 1, delay 2, delay 3 : std_logic; begin process(clr, cclk) begin if(clr='1') then delay 1<='0'; delay 2<='0'; delay 3<='0'; elsif(rising_edge(cclk)) then delay 1<=inp; delay 2<=delay 1; delay 3<=delay 2; end if; end process; outp<=delay 1 and delay 2 and (not delay 3); end Behavioral;

数字逻辑单元设计-脉冲宽度调制设计 PWM控制电机的VHDL语言描述 library IEEE; process(clk, clr) use IEEE. STD_LOGIC_1164. ALL; begin use IEEE. STD_LOGIC_ARITH. ALL; if(clr='1') then use IEEE. STD_LOGIC_UNSIGNED. ALL; count<="0000"; entity pwm 4 is elsif(rising_edge(clk)) then Port ( if(count=period 1 -1) then clk : in STD_LOGIC; count<="0000"; clr : in STD_LOGIC; else duty : in STD_LOGIC_VECTOR (3 downto 0); count<=count + 1; period 1 : in STD_LOGIC_VECTOR (3 downto 0); end if; pwm : out STD_LOGIC); end if; end pwm 4; end process; architecture Behavioral of pwm 4 is signal count : STD_LOGIC_VECTOR (3 downto 0); signal set, reset : std_logic; Begin set <= not (count(0) or count(1) or count(2) or count(3));

数字逻辑单元设计-脉冲宽度调制设计 process(clk) begin if(rising_edge(clk)) then if(count=duty) then reset<='1'; else reset<='0'; end if; end process; process(clk) begin if(rising_edge(clk)) then if(set='1') then pwm<='1'; end if; if(reset='1') then pwm<='0'; end if; end process; end Behavioral;

数字逻辑单元设计-ＲＯＭ设计 library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_unsigned. all; entity rams_21 a is port (clk : in std_logic; en : in std_logic; addr : in std_logic_vector(5 downto 0); data : out std_logic_vector(19 downto 0)); end rams_21 a;

数字逻辑单元设计-ＲＯＭ设计 architecture syn of rams_21 a is type rom_type is array (63 downto 0) of std_logic_vector (19 downto 0); signal ROM : rom_type: = (X"0200 A", X"00300", X"08101", X"04000", X"08601", X"0233 A", X"00300", X"08602", X"02310", X"0203 B", X"08300", X"04002", X"08201", X"00500", X"04001", X"02500", X"00340", X"00241", X"04002", X"08300", X"08201", X"00500", X"08101", X"00602", X"04003", X"0241 E", X“ 00301”, X"00102", X"02122", X"02021", X"00301", X"00102", X"02222", X"04001", X"00342", X"0232 B", X"00900", X"00302", X"00102", X"04002", X"00900", X"08201", X"02023", X"00303", X"02433", X"00301", X"04004", X"00301", X"00102", X"02137", X"02036", X"00301", X"00102", X"02237", X"04004", X"00304", X"04040", X"02500", X"0030 D", X"02341", X"08201", X"0400 D");

数字逻辑单元设计-ＲＯＭ设计 begin process (clk) begin 　if rising_edge(clk) then 　　if (en = '1') then 　　　data <= ROM(conv_integer(addr)); 　　end if; end process; end syn;

数字逻辑单元设计-RAM设计 library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_unsigned. all; entity rams_01 is port (clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(5 downto 0); di : in std_logic_vector(15 downto 0); do : out std_logic_vector(15 downto 0)); end rams_01; architecture syn of rams_01 is 　type ram_type is array (63 downto 0) of 　std_logic_vector (15 downto 0); 　signal RAM: ram_type; begin 　process (clk) 　begin 　if clk'event and clk = '1' then 　　if en = '1' then 　　　if we = '1' then 　　　RAM(conv_integer(addr)) <= di; 　　　end if; 　　　do <= RAM(conv_integer(addr)) ; 　　end if; 　end process; end syn;

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FSM的分类--Moore状态机 Moore型序列检测器的VHDL语言描述 library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity seqdeta is port( clk : in std_logic; clr : in std_logic; din : in std_logic; dout : out std_logic ); end seqdeta; architecture Behavioral of seqdeta is type state is(s 0, s 1, s 2, s 3, s 4); ---状态声明 signal present_state, next_state : state; begin process(clr, clk) begin if(clr='1') then --状态寄存器 present_state<=s 0; elsif rising_edge(clk) then present_state<=next_state; end if; end process;

FSM的分类--Moore状态机 process(present_state, din) --下状态转移逻辑 begin when s 3=> case present_state is if(din='1') then when s 0=> next_state<=s 4; if(din='1') then else next_state<=s 1; next_state<=s 0; else end if; next_state<=s 0; when s 4=> end if; if(din='0') then when s 1=> next_state<=s 0; if(din='1') then else next_state<=s 2; else end if; next_state<=s 0; when others=> end if; next_state<=s 0; when s 2=> end case; if(din='0') then end process; next_state<=s 3; else next_State<=s 2; end if;

FSM的分类--Moore状态机 process(present_state) begin if(present_state=s 4) then dout<='1'; else dout<='0'; end if; end process; end Behavioral; --输出逻辑和当前输入无关

FSM的分类--Mealy型状态机 library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity seqdetb is port( clk : in std_logic; clr : in std_logic; din : in std_logic; dout : out std_logic ); end seqdetb; architecture Behavioral of seqdetb is type state is(s 0, s 1, s 2, s 3); --定义状态 signal present_state, next_state : state; begin process(clr, clk) --状态寄存器 begin if(clr='1') then present_state<=s 0; elsif rising_edge(clk) then present_state<=next_state; end if; end process;

FSM的分类--Mealy型状态机 process(present_state, din) --状态转移逻辑 begin case present_state is when s 0=> if(din='1') then next_state<=s 1; else next_state<=s 0; end if; when s 1=> if(din='1') then next_state<=s 2; else next_state<=s 0; end if; when s 2=> if(din='0') then next_state<=s 3; else next_State<=s 2; end if; when s 3=> if(din='1') then next_state<=s 1; else next_state<=s 0; end if; when others=> next_state<=s 0; end case; end process;

FSM的分类--Mealy型状态机 process(clr, clk) --输出逻辑和当前输入有关 begin if(clr='1') then dout<='0'; elsif rising_edge(clk) then if(present_state=s 3 and din='1') then dout<='1'; else dout<='0'; end if; end process;