library ieee use ieee stdlogic1164 all entity example

编程： library ieee; use ieee. std_logic_1164. all; entity example 1 is port(A 1, B 1, A 2, B 2, A 3, B 3, A 4, B 4 : in std_logic; Y 1, Y 2, Y 3, Y 4 : out std_logic); end example 1; architecture e 1 of example 1 is begin Y 1 <= A 1 nand B 1 after 10 ns; Y 2 <= A 2 nand B 2 after 10 ns; Y 3 <= A 3 nand B 3 after 10 ns; Y 4 <= A 4 nand B 4 after 10 ns; end e 1; 本例用并行语句，表示 10 ns后，4个输出都应同时出现输入逻辑运算结果。这 是因ASIC器件是一个 4与非电路，一旦加入输入信号，则输出立即反映。

编程： library ieee; use ieee. std_logic_1164. all; entity example 1 is port(A 1, B 1, A 2, B 2, A 3, B 3, A 4, B 4 : in std_logic; Y 1, Y 2, Y 3, Y 4 : out std_logic); end example 1; architecture e 2 of example 1 is begin Y 1 <= A 1 nor B 1 after 10 ns; Y 2 <= A 2 nor B 2 after 10 ns; Y 3 <= A 3 nor B 3 after 10 ns; Y 4 <= A 4 nor B 4 after 10 ns; end e 2; 本例用并行语句，表示 10 ns后，4个输出都应同时出现输入逻辑运算结果。这 是因ASIC器件是一个 4或非电路，一旦加入输入信号，则输出立即反映。(0/1)

编程： library ieee; use ieee. std_logic_1164. all; entity example 1 is port(A : in std_logic_vector((n – 1) downto 0); F : out std_logic); end example 1; architecture e 3 of example 1 is begin process(A) variable TEMP_F : bit; begin TEMP_F : =‘ 1’; for i in 0 to A’length loop TEMP_F : = TEMP_F and A(i); end loop; F <= not TEMP_F; end process; end e 3;

library ieee; use ieee. std_logic_1164. all; entity HC 85 is port(A, B : in std_logic_vector(3 downto 0); EO, GO, LO : out std_logic); end HC 85; architecture behavioral of HC 85 is begin if (A > B) then GO <= ‘ 1’ after 10 ns; EO <= ‘ 0’ after 10 ns; LO <= ‘ 0’ after 10 ns; elsif (A < B) then LO <= ‘ 1’ after 10 ns; EO <= ‘ 0’ after 10 ns; GO <= ‘ 0’ after 10 ns; els EO <= ‘ 1’ after 10 ns; EO <= ‘ 0’ after 10 ns; LO <= ‘ 0’ after 10 ns; end if; end behavioral;

port(A, B : in std_logic_vector(3 downto 0); EI, GI, LI : in std_logic； _ _低位比较的三种结果 EO, GO, LO : out std_logic); begin if (A > B) then GO <= ‘ 1’ after 10 ns; EO <= ‘ 0’ after 10 ns; LO <= ‘ 0’ after 10 ns; elsif (A < B) then LO <= ‘ 1’ after 10 ns; EO <= ‘ 0’ after 10 ns; GO <= ‘ 0’ after 10 ns; else if (EI = ‘ 1’ then EO <= ‘ 1’ after 10 ns; LO <= ‘ 0’ after 10 ns; GO <= ‘ 0’ after 10 ns; elsif(GI = ‘ 1’ then EO <= ‘ 0’ after 10 ns; LO <= ‘ 0’ after 10 ns; GO <= ‘ 1’ after 10 ns; elsif(LI = ‘ 1’ then EO <= ‘ 0’ after 10 ns; LO <= ‘ 1’ after 10 ns; GO <= ‘ 0’ after 10 ns; end if;

例：设计一个将8421编码转换成 2421和余 3代码功能部件 library ieee; use ieee. std_logic_1164. all; entity example is port(i_code : in std_logic_vector(3 downto 0); cflag : in std_logic; o 2421_code : out std_logic_vector(3 downto 0); o 3_code : out std_logic_vector(3 downto 0)); end example; architecture e 4 of example is begin o 2421_code <= i_code when(i_code <= “ 0100” and cflag = ‘ 0’) else i_code + 6 when(i_code >=“ 0101” and i_code <=“ 1001”) else ‘Z’ when other; o 3_code <= i_code + 3 when(i_code <= “ 1001” and cflag = ‘ 1’) else ‘Z’ when other; end e 4;

例： 4选1多路选择器的主干程序为： entity example is port(d 0, d 1, d 2, d 3 : in std_logic; a 0 a 1 a 0, a 1 : in std_logic; q : out std_logic); end example; architecture e 5 of example is signal sel : integer; begin with select q <= d 0 after 10 ns when 0, d 1 after 10 ns when 1, d 2 after 10 ns when 2, d 3 after 10 ns when 3, ‘x’ after 10 ns when other; sel <= 0 when a 0 =‘ 0’ and a 1 =‘ 0’ else 1 when a 0 =‘ 1’ and a 1 =‘ 0’ else 2 when a 0 =‘ 0’ and a 1 =‘ 1’ else 3 when a 0 =‘ 1’ and a 1 =‘ 1’ else 4; end e 5; d 0 d 1 d 2 d 3 q

例： 4选1多路分配器的主干程序为： entity example is a 0 a 1 d port(d : in std_logic; a 0, a 1 : in std_logic; q 0, q 1, q 2, q 3 : out std_logic); q 0 q 1 q 2 q 3 end example; architecture e 6 of example is signal sel : integer; begin with select q 0 <= d after 10 ns when 0; q 1 <= d after 10 ns when 1; q 2 <= d after 10 ns when 2; q 3 after 10 ns when 3; sel <= 0 when a 0 =‘ 0’ and a 1 =‘ 0’ else 1 when a 0 =‘ 1’ and a 1 =‘ 0’ else 2 when a 0 =‘ 0’ and a 1 =‘ 1’ else 3 when a 0 =‘ 1’ and a 1 =‘ 1’ else 4; end e 6;

半加器主干程序为： entity example is port(a, b : in std_logic; sum, carry : out std_logic); end example; architecture e 7 of example is signal c, d : std_logic; begin c <= a or b; --a、b任一为 1， c 为 1 d <= a nand b; --a、b都为 1时，d 为 0，否则 d 为 1 carry <= not d; --d=0，carry=1，满足此条件只有a、b同为 1 sum <= c and d; --sum=1，只有a、b任中为 1并与d为 1 end e 7;

全加器主干程序为： entity example is port(AI, BI, CIN : in std_logic; SI, CI : out std_logic); end example; architecture e 8 of example is begin SI <= (AI xor BI) xor CIN; CI <= (AI and BI) or (CIN and AI) or (CIN and BI); end e 8;

4位加/减器主干程序为： entity example is port(a, b : in std_logic_vector(3 downto 0); a_sflag : in std_logic; _ _加、减法控制变量 q : out std_logic_vector(4 downto 0)); end example; architecture e 9 of example is begin process(a, b, a_sflag) begin if a_sflag = ‘ 1’ then q <= (‘ 0’&a) + b; else q <= (‘ 0’&a) – b; end if; end process; end e 9;

字节求补器主干程序为： entity example is port(a : in std_logic_vector(7 downto 0); y : out std_logic_vector(7 downto 0)); end example; architecture e 10 of example is begin y <= not(a) + 1; end e 10;

双2 – 4线译码器主干程序为： entity example is port(a 2, b 2, g 2, a 1, b 1, g 1 : in std_logic; y 20, y 21, y 22, y 23, y 10, y 11, y 12, y 23 : out std_logic); end example; architecture e 11 of example is begin y 10 <= ‘ 0’ when (b 1 = ‘ 0’) and ((a 1=‘ 0’) and (g 1 = ‘ 0’)) else ‘ 1’; y 11 <= ‘ 0’ when (b 1 = ‘ 0’) and ((a 1=‘ 1’) and (g 1 = ‘ 0’)) else ‘ 1’; y 12 <= ‘ 0’ when (b 1 = ‘ 1’) and ((a 1=‘ 0’) and (g 1 = ‘ 0’)) else ‘ 1’; y 13 <= ‘ 0’ when (b 1 = ‘ 1’) and ((a 1=‘ 1’) and (g 1 = ‘ 0’)) else ‘ 1’; y 20 <= ‘ 0’ when (b 2 = ‘ 0’) and ((a 2=‘ 0’) and (g 2 = ‘ 0’)) else ‘ 1’; y 21 <= ‘ 0’ when (b 2 = ‘ 0’) and ((a 2=‘ 1’) and (g 2 = ‘ 0’)) else ‘ 1’; y 22 <= ‘ 0’ when (b 2 = ‘ 1’) and ((a 2=‘ 0’) and (g 2 = ‘ 0’)) else ‘ 1’; y 23 <= ‘ 0’ when (b 2 = ‘ 1’) and ((a 2=‘ 1’) and (g 2 = ‘ 0’)) else ‘ 1’; end e 11;

3 – 8线译码器主干程序为： entity example is port(a, b, c : in std_logic; y : out std_logic_vector(7 downto 0)); end example; architecture e 12 of example is signal x : std_logic_vector(2 downto 0); begin x <= a & b & c case x is when 000 => y <= 11111110; when 001 => y <= 11111101; when 010 => y <= 11111011; when 011 => y <= 11110111; when 100 => y <= 11101111; when 101 => y <= 11011111; when 110 => y <= 10111111; when 111 => y <= 01111111; end case; end e 12;

地址译码器主干程序为： entity example is port(en : in std_logic; adr : in std_logic_vector(19 downto 0); cs : out std_logic_vector(3 downto 0)); end example; architecture e 13 of example is begin cs(0) <= ‘ 0’when((en =‘ 0’)and(adr >= X” 00000”)and(adr <= X” 01 FFF”))) else ‘ 1’; cs(1) <= ‘ 0’when((en =‘ 0’)and(adr >= X” 40000”)and(adr <= X” 43 FFF”))); else ‘ 1’; cs(2) <= ‘ 0’when((en =‘ 0’)and(adr >= X” 08000”)and adr <= X” 0 AFFF”))); else ‘ 1’; cs(3) <= ‘ 0’when((en =‘ 0’)and(adr >= X”E 0000”)and(adr <= X”E 01 FF”))); else ‘ 1’; end e 13;

三态总线主干程序为： entity example is port(my_in : in std_logic_vector(7 downto 0); sel : in std_logic; my_out : out std_logic_vector(7 downto 0)); end example; architecture e 14 of example is begin my_out <= “ZZZZ” when (sel = ‘ 1’) else my_in; end e 14;

总线收发器主干程序为： entity example is port(A, B : inout std_logic_vector(7 downto 0); DR, EN : in std_logic); end example; architecture e 15 of example is begin A <= B when (EN = ‘ 0’) and (DR = ‘ 0’) else (other => ‘Z’); B <= A when (EN = ‘ 0’) and (DR = ‘ 1’) else (other => ‘Z’); end e 15;

library ieee； use ieee. std_logic_1164. all； entity example LED is port ( clk，dps_in ：in std_logic； dpd_in ：in std_logic_vector ( 7 downto 0 )； led 1，led 2，led 3，led 4 ：out std_logic； dpd_out ：out std_logic_vector ( 7 downto 0 ) )； end example LED； architecture LED of example is variable temp ：std_logic_vector ( 7 downto 0 )； 下面用选择信号代入语句来实现显示功能： with 选择条件表达式 select 目标信号 <= 表达式 1 when 选择条件 1， 表达式 2 when 选择条件 2， … 表达式n when 选择条件n；

begin p 1： process ( clk )； if clk’event and clk =‘ 1’and dps_in =‘ 1’then temp < = dpd_in； end if； led 1 < =‘ 0’ with temp select dpd_out <=“ 11111100”when“ 0”， “ 01100000”when“ 1”， “ 11011010”when“ 2”， “ 11110010”when“ 3”， “ 0110”when“ 4”， “ 10110110”when“ 5”， “ 10111110”when“ 6”， “ 11100000”when“ 7”， “ 11111110”when“ 8”， “ 11110110”when“ 9”，

led 2 <=‘ 0’； with temp select dpd_out <=“ 11111100”when“ 0”， “ 01100000”when“ 1”， “ 11011010”when“ 2”， “ 11110010”when“ 3”， “ 0110”when“ 4”， “ 10110110”when“ 5”， “ 10111110”when“ 6”， “ 11100000”when“ 7”， “ 11111110”when“ 8”， “ 11110110”when“ 9”，

led 3 <=‘ 0’； with temp select dpd_out <=“ 11111101”when“ 0”， “ 01100001”when“ 1”， “ 11011011”when“ 2”， “ 11110011”when“ 3”， “ 01100111”when“ 4”， “ 10110111”when“ 5”， “ 10111111”when“ 6”， “ 11100001”when“ 7”， “ 1111”when“ 8”， “ 11110111”when“ 9”，

led 4 <=‘ 0’； with temp select dpd_out <=“ 11111100”when“ 0”， “ 01100000”when“ 1”， “ 11011010”when“ 2”， “ 11110010”when“ 3”， “ 0110”when“ 4”， “ 10110110”when“ 5”， “ 10111110”when“ 6”， “ 11100000”when“ 7”， “ 11111110”when“ 8”， “ 11110110”when“ 9”， end process p 1； end LED；

12位寄存器主干程序为： entity example is port(D : in std_logic_vector(11 downto 0); CLK : in std_logic; Q : out std_logic_vector(11 downto 0)); end example; architecture e 16 of example is begin process begin wait until CLK = ‘ 1’; Q <= D; end process; end e 16;

三态输出 8 D寄存器主干程序为： entity example is port(data : in std_logic_vector(7 downto 0); clk, oe : in std_logic; qout : out std_logic_vector(7 downto 0)); end example; architecture e 17 of example is signal qint : std_logic_vector(7 downto 0); begin qint <= data when rising_edge(clk); qout <= qint when oe = ‘ 0’’ else “ZZZZ”; end e 17;

并行装载 8位减 1计数器主干程序为： entity example is port(datain : in std_logic_vector(7 downto 0); clk, load : in std_logic; q : out std_logic_vector(7 downto 0); tc : out std_logic); end example; architecture e 18 of example is signal count : std_logic_vector(7 downto 0); begin wait until rising_edge(clk); if load = ‘ 1’ then count <= datain; else count <= count – 1; end if; tc <= ‘ 1’ when count = “ 0000” else ‘ 0’; q <= count; end e 18;

十进制加法计数器主干程序为： entity example is port(clk, rst, en : in std_logic; cout : out std_logic; cq : out std_logic_vector(3 downto 0)); end example; architecture e 19 of example is begin process (clk, rst, en); variable cqi : std_logic_vector(3 downto 0); begin if rst = ‘ 1’ then cqi : = ‘ 0’; elsif clk’event and clk = ‘ 1’ then if en = ‘ 1’ then if cqi < “ 1001” then cqi : = cqi + 1; else cqi : = ‘ 0’; end if; if cqi = “ 1001” then cout<=‘ 1’; else cout<=‘ 0’; end if; cq <= cqi; end process; end e 19;

并行输入串行输出移位寄存器主干程序为： entity example is port(clk, load, en : in std_logic; --en是清除而load是装载(皆低有效)、clk时钟 di : in std_logic_vector(7 downto 0); do : out std_logic); end example; architecture e 20 of example is variable q : std_logic_vector(7 downto 0); begin p 1: process (clk, load, en); if en = ‘ 0’ then q <= “ 0000”; do <= ‘ 0’; elsif clk’event and clk = ‘ 1’ then if load = ‘ 0’ then q <= di; do <= ‘ 0’; _ _并行装载 else do <= q(7); _ _最高位输出 end if; for i in 1 to 7 loop q(i) <= q(i – 1); end loop; end if; end process p 1; end e 20;

串行输入并行输出移位寄存器主干程序为： entity example is port(clk, load, din, en : in std_logic; dout: out std_logic_vector (7 downto 0)); end example; architecture e 21 of example is variable q : std_logic_vector(7 downto 0); begin process (clk); begin if clk’event and clk = ‘ 1’ then q(0) <= di; for i in 1 to 7 loop q(i) <= q(i - 1); //左移 end loop; end if; end process; dout<= q; end e 21;

串行输入串行输出移位寄存器主干程序为： entity example is port(clk, load, din : in std_logic; dout: out std_logic); end example; architecture e 22 of example is variable q : std_logic_vector(7 downto 0); begin process (clk, load, en); begin if load = ‘ 0’ then q <= “ZZZZ”; elsif clk’event and clk = ‘ 1’ then q(0) <= din; for i in 1 to 7 loop q(i) <= q(i - 1); end loop; end if; dout <=q(7); end process; end e 22;

并行输入串行输出移位寄存器主干程序为： entity example is port(clk, load: in std_logic; din: in std_logic_vector(7 downto 0) dout : out std_logic; end example; architecture e 23 of example is variable q : std_logic_vector(7 downto 0); begin process (clk, load); begin if load = ‘ 0’ then q <= “ZZZZ”; elsif clk’event and clk = ‘ 1’ then q<=din; else for i in 1 to 7 loop q(i) <= q(i - 1); end loop; end if; dout <=q(7); end process; end e 23;