4 VHDL library ieee use ieee stdlogic1164 all

4. VHDL • • 가산/감산 library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_signed. all; • • • entity ma is port(add : in std_logic; a : in std_logic_vector(2 downto 0); b : in std_logic_vector(1 downto 0); re : out std_logic_vector(3 downto 0)); end ma; • • • architecture func of ma is begin re<=a+b when add='0' else a-b; end func;

4. VHDL • • 디코더로 결과값 출력 library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_unsigned. all; • • • entity ten is port(add : in std_logic; a : in std_logic_vector(2 downto 0); b : in std_logic_vector(1 downto 0); res : out std_logic_vector(6 downto 0)); end ten; • • architecture func of ten is signal u : std_logic_vector(3 downto 0); component ma port(add : in std_logic; a : in std_logic_vector(2 downto 0); b : in std_logic_vector(1 downto 0); re : out std_logic_vector(3 downto 0)); end component;

4. VHDL • • • • begin w 1 : ma port map(add, a, b, u); with u select res<="0000001" when "0000", "1001111" when "0001", "0010010" when "0010", "0000110" when "0011", "1001100" when "0100", "0100100" when "0101", "0100000" when "0110", "0000010" when "0111", "0000000" when "1000", "0000100" when "1001", "0000001" when others; end func;